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? semiconductor components industries, llc, 2015 january, 2015 ? rev. 14 1 publication order number: NOIH2SM1000A/d NOIH2SM1000A has2 image sensor introduction scope this datasheet details the ratings, physical, geometrical, electrical and electro-optical characteristics, and test- and inspection-data for the high accuracy star t racker (has2) cmos active pixel image sensor (cmos aps). the device described in this document is protected by us patent 6,225,670 and others. component type values table 10 on page 9 provides a summary of the type variants. the complete list of specifications for each type variant is given in the specifications tables. all specifications are given at 22 3 c, under nominal clocking and bias conditions. exceptions are noted in the ?remarks? field. maximum rating table 11 on page 9 specifies the maximum ratings. do not exceed these ratings at any times, during use or storage. physical dimension and geometrical information figure 4 on page 24 shows the physical dimensions of the assembled component. the geometrical information in figure 3 on page 10 describes the position of the die in the package. pin assignment figure 25 on page 39 contains the pin assignment. the figure contains a schematic drawing and a pin list. a detailed functional description of each pin is available in pin list on page 35. soldering instructions soldering is restricted to manual soldering only. no wave or reflow soldering is allowed. for manual soldering, the following restrictions are applicable: ? solder 1 pin on each of the four sides of the sensor. ? cool down for a minimum period of 1 minute before soldering another pin on each of the four sides. ? repeat soldering of 1 pin on each side, including a 1 minute cool down period. handling precautions the component is susceptible to damage by electro-static discharge. therefore, use suitable precautions for protection during all phases of manufacture, testing, packaging, shipment, and any handling. follow these guidelines: ? always manipulate devices in an esd controlled environment. ? always store the devices in a shielded environment that protects against esd damage (at least a non-esd generating tray and a metal bag). ? always wear a wrist strap when handling the devices and use esd safe gloves. ? the has2 is classified as class 1a (jedec classification - [ad02]) device for esd sensitivity. for proper handling and storage conditions, refer to the on semiconductor application note an52561. return material authorization (rma) on semiconductor packages its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. storage information the components must be stored in a dust-free and temperature-, humidity-and esd-controlled environment. ? store devices in special esd-safe trays such that the glass window is never touched. ? close the trays with eds-safe rubber bands. ? seal the trays in an esd-safe conductive foil in clean room conditions. ? for transport and storage outside a clean room, pack the trays in a second esd-save bag that is sealed in clean room. additional information the has sensor is subject to the standard european export regulations for dual use products. a certificate of conformance will be issued upon request at no additional charge. the coc refers to this datasheet version. itar information all the has2 type variants are itar-free components. www.onsemi.com
NOIH2SM1000A www.onsemi.com 2 table 1. ordering information marketing part number description package noih2sm1000t-hhc has2 mono, flight model, level 2 84-pin jlcc NOIH2SM1000A-hhc has2 mono, engineering model noih2sm1000s-hhc has2 mono, flight model, level 1 NOIH2SM1000A-hwc has2 mono windowless, engineering model noih2sm1000s-hwc has2 mono windowless, flight model, level 1 ordering code definition for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . applicable documents the following documents form part of this specification: table 2. applicable documents no. reference title ad01 npd ? 0064422 image sensor characterization standard ad02 jesd22-a114-b electrostatic discharge (esd) sensitivity testing human body model (hbm) ad03 12mbe83443f process identification document for has2 ad04 12mon56972e visual inspection for fm devices 1. lot acceptance and screening are based on escc 9020. please note that lot acceptance and screening on page 6 ? is valid for the flight model level 1 devices. for more information on flight model 1 windowless devices, please contact imagesensors@onsemi.com
NOIH2SM1000A www.onsemi.com 3 detailed information deviations from generic specification lot acceptance and screening are based on escc 9020. see lot acceptance and screening on page 6 and document npd ? 0067186 for more information. mechanical requirements dimension check the dimensions of the components specified here is checked and must comply with the specifications and the tolerances indicated in figure 4 on page 24 geometrical characteristics the geometrical characteristics of the components specified here is checked and must comply with the specifications and tolerances given in figure 4 on page 24 and figure 3 on page 10 mass the maximum mass of the components specified here is specified in table 14 on page 10 materials and finishes the materials and finishes is as specified in this document. where a definite material is not specified, a material which enables the components to meet the performance requirements of this specification must be used. case the case is hermetically sealed and must have a ceramic body and a glass window. table 3. case type jlcc ? 84 material black alumina ba ? 914 thermal expansion coefficient 7.6 x 10 ? 6/k hermeticity < 5 x 10 ? 7 atms. cm 3 /s thermal resistance (junction to case) 3.633 c/w lead material and finish table 4. lead material and finish lead material kovar 1e finish nickel, min 2 m 2 nd finish gold, min 1.5 m window the window material is a bk7g18 glass lid with anti-reflective coating applied on both sides. the optical quality of the glass must have the specifications in table 15 on page 11. the anti reflective coating has a reflection coef ficient less than 1.3% absolute and less than 0.8% on average, over a bandwidth from 440 nm to 1100 nm. level 2 versus level 1 differences has2 flight model level 2 devices differ from level 1 devices in lot acceptance and screening tests: ? 100% screening is applied with burn-in limited to 168 h ? devices will be fully tested at room temperature and 85 c. ? x/y die placement is relaxed to 200 m. ? mismatching between odd and even columns in destructive readout is allowed but shall stay in the limit of 127 lsb. ? the defect and particles specification will be the same as for the engineering model - NOIH2SM1000A-hhc ? with the exception of the defective columns which are not allowed in the level 2 devices. refer to table 10 ?type variant summary? on page 9. ? endurance testing during wafer lat is limited to a 1000 h burn in and will be performed on 3 un screened parts. ? prior to endurance testing and total dose testing, a stabilization bake of 48 hrs, followed by a 168 hrs burn-in, shall be performed. ? during wafer lat, the electro-optical measurements are limited on 2 parts (1 from endurance and 1 from radiation testing). ? for each assembly batch (manufacturing-lot), 2 screened devices will be made available for a dpa test. an assembly batch is defined as a group of parts which have been assembled within a time window of less than one week. the dpa devices can be rejected devices (glass lid cosmetic defects, electrical defects, ) but have to be screened through the same thermal steps as the has2 ?level2?. the dpa test will be carried out by on semiconductor as a customer courtesy. prior to dpa testing, the following tests are performed: solderability and resistance to solvents (marking permeability). note: as the glass lid removal is a best effort activity, the dpa test cannot be 100% guaranteed. ? assembly lot acceptance testing is not performed.
NOIH2SM1000A www.onsemi.com 4 data pack each set of devices will have a data pack which will be made available to the customer. the data pack consists of: ? coc form referring to the applicable specification ? calibration data ? screening report ? life test report and radiation (total dose) test report for each wafer lot ? electrical test report ? spectral response data ? visual inspection report ? dpa test report marking general the marking must consist of lead identification and traceability information. lead identification an index to pin 1 must be located on the top of the package in the position defined in figure 4 on page 24. the pin numbering is counter clock-wise, when looking at the top-side of the component. traceability information each component must be marked such that complete traceability is maintained. the component must have a number as follows: figure 1. product marking xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week nnnn = serial number 53 33 12 32 74 54 75 11 84 1 table 5. package mark decoder orderable part number package mark: line 1 package mark: line 2 package mark: line 3 noih2sm1000t-hhc noih2sm1000t -hhc nnnn awlyyww NOIH2SM1000A-hhc NOIH2SM1000A -hhc nnnn awlyyww noih2sm1000s-hhc noih2sm1000s -hhc nnnn awlyyww NOIH2SM1000A-hwc NOIH2SM1000A -hwc nnnn awlyyww noih2sm1000s-hwc noih2sm1000s -hwc nnnn awlyyww where nnnn- serialized number controlled manually by on semiconductor, belgium where dd-mm-yyyy represents the lot assembly date noih2sm1000t-hhc has a minimum order quantity of 10 electrical and electro ? optical measurements electrical and electro ? optical measur ements at reference temperature the parameters to be measured to verify the electrical and electro-optical specifications are given in table 18 on page 14 and table 27 on page 23. unless otherwise specified, the measurements must be performed at a environmental temperature of 22 3 c. for all measurements, the nominal power supply, bias, and clocking conditions apply. the nominal power supply and bias conditions are given in table 28 on page 23; the timing diagrams in figure 35 on page 46 and figure 37 on page 48. note: the given bias and power supply settings imply that the devices are measured in ?soft-reset? condition. electrical and electro ? optical measur ements at high and low temperature table 19 on page 15 and table 20 on page 16 list the parameters to be measured to verify electrical and electro-optical specifications. unless otherwise specified,
NOIH2SM1000A www.onsemi.com 5 the measurements must be performed at ?40 (?5 +0) c and at +85 (+5 ?0) c. circuits for electrical and electro ? optical measur ements circuits for performing the electro ? optical tests in table 18 on page 14 and table 27 on page 23 are shown in figure 49 on page 58 to figure 52 on page 58. burn ? in test parameter drift values the parameter drift values for power burn-in are specified in table 21 on page 17. unless otherwise specified, the measurements must be conducted at an environmental temperature of 22 3 c and under nominal power supply, bias, and timing conditions. in addition to the drift value requirements, the devices do not exceed the limit values of any parameter, as indicated in table 18 on page 14. conditions for high temperature reverse bias burn-in not applicable conditions for power burn-in the conditions for power burn-in is specified in table 24 on page 19 of this specification. electrical circuits for high temperature reverse bias burn-in not applicable electrical circuits for power burn-in circuits to perform the power burn-in test are shown in figure 48 on page 57 and figure 49 on page 58 of this specification. environmental and endurance tests electrical and electro-optical measurements on completion of environmental test the parameters to be measured on completion of environmental tests are listed in table 25 on page 20. unless otherwise stated, the measurements must be performed at a environmental temperature of 22 3 c. measurements of dark current must be performed at 22 1 c and the actual environmental temperature must be reported with the test results. electrical and electro-optical measurements at intermediate point during endurance test the parameters to be measured at intermediate points during endurance test of environmental tests are listed in table 25 on page 20. unless otherwise stated, the measurements must be performed at an environmental temperature of 22 3 c. electrical and electr o-optical measur ements on completion of endurance test the parameters to be measured on completion of endurance tests are listed in table 25 on page 20. unless otherwise stated, the measurements must be performed at a environmental temperature of 22 3 c. conditions for operating life test the conditions for operating life tests must be as specified in table 24 on page 19 of this specification. electrical circuits for operating life test circuits for performing the operating life test are shown in figure 49 on page 58 and next ones of this specification. conditions for high temperature storage test the temperature to be applied must be the maximum storage temperature specified in table 11 on page 9 of this specification.
NOIH2SM1000A www.onsemi.com 6 total dose radiation test application the total dose radiation test must be performed in accordance with the requirements of escc basic specification 22900. parameter drift values the allowable parameter drift values after total dose irradiation are listed in t able 22 on page 18 . the parameters shown are valid after a total dose of 50 krad and 168 h / 100 c annealing. bias conditions continuous b ias must be applied during irradiation testing as shown in figure 49 on page 58 and next ones of this specification. electrical and electro-optical measurements the parameters to be measured, prior to, during and on completion of the irradiation are listed in table 27 on page 23 of this specification. only devices that meet the specification in table 18 on page 14 of this specification must be included in the test samples. lot acceptance and screening this section describes the lot acceptance testing (lat) and screening on the has2 fm devices. all tests on device level must be performed on screened devices (see table 9 on page 7) wafer lot acceptance this is the acceptance of the silicon wafer lot. this must be done on every wafer lot that is used for the assembly of flight models. table 6. test test method number of devices test condition wafer processing data review pid na na sem escc 21400 4 naked dies na total dose test escc 22900 3 devices 50 krad, not to exceed 3.6 krad/hr endurance test mil-std-883 method 1005 6 devices 2000h at +125 c before and after total dose test and endurance test: ? electrical measurements before and after at high, low, and room temperature. see table 18 on page 14, table 19 on page 15 and table 20 on page 16 of this specification. ? visual inspection before and after ? detailed electro-optical measurements before and after glass lot acceptance transmission and reflectance curves that are delivered with each lot must be compared with the specifications in table 15. three glass lids are chosen randomly from the lot and measured in detail. the results are compared with figure 5 on page 25. package lot acceptance ? five packages are chosen randomly from the lot and measured in detail. the results are compared with figure 4 on page 24. ? a solderability test is covered in the assembly lot acceptance tests (table 7) table 7. assembly lot acceptance test test method number of devices test condition special assembly house in process control bond strength test mil-std-883 method 2011 2 d assembly house geometrical data review review all solder ability mil-std883, method 2003 3 d terminal strength mil-std 883, method 2004 marking permanence escc 24800 geometrical measurements 12mbe83937f 5 temperature cycling mil-std 883, method 1010 5 condition b 50 cycles ?55 c / +125 c moisture resistance jedec std. method a101-b 240 h at 85 c / 85% temperature cycling around dew point escc9020 8.15(a) phase 2 5 phase 2
NOIH2SM1000A www.onsemi.com 7 table 7. assembly lot acceptance test test condition number of devices test method residual gas analysis mil-std-883, method 1018 2 procedure 1 dpa die shear test mil-std-883, method 2019 4 n/a bond pull test mil-std-883, method 2011 all wires notes: as the glass lid is removed from the package prior to dpa, the results of the dpa cannot be guaranteed. has2 does not comply with the moisture limit of escc9020 ? see document npd ? 0067186. before and after the following tests are done: ? electrical measurements conform to table 18 on page 14 of this specification ? detailed visual inspection ? fine leak test + gross leak test fine- and gross-leak tests must be performed using the following methods: fine leak test : mil-std-883, test method 1014, condition a, 30 psi for 24 h gross leak test : mil-std-883, test method 1014, condition c, 30 psi for 24 h the required leak rate for fine leak testing is 5x10 ? 7 atms.cm 3 /s table 8. periodic testing test test method number of devices test condition mechanical shock mil-std 883, method 2002 2 b - 5 shocks, 1500 g ? 0.5 ms ? ? sine, 6 axes mechanical vibration mil-std 883, method 2007 2 a - 4 cycles, 20 g 80 to 2000 hz, 0.06 inch 20 to 80 hz, 3 axes dpa die shear test mil-std-883 method 2019 2 n/a bond pull test mil-std-883 method 2011 all wires note: as the glass lid is removed from the package prior to dpa, the results of the dpa cannot be guaranteed. periodic testing is required every two years. before and after the following tests are done: ? electrical measurements conform to table 18 on page 14 ? detailed visual inspection ? fine leak test + gross leak test fine- and gross-leak tests must be performed using the following methods: fine leak test : mil-std-883, test method 1014, condition a, 30 psi for 24 h gross leak test : mil-std-883, test method 1014, condition c, 30 psi for 24 h the required leak rate for fine leak testing is 5x10 7 atms.cm 3 /s table 9. screening no. test test method number of devices test condition 1 stabilization bake mil-std-883 method 1008 all 48h at 125 c 2 hcrt electrical measurements 12mbe83443f all ht +85 c lt ?40 c rt +22 c 3 visual inspection 12mon56972e all 4 die placement measurements 12mbe83937f all 5 xray escc 20900 all 6 fine leak test mil-std-883 method 1014 all a 7 gross leak test mil-std-883 method 1014 all c
NOIH2SM1000A www.onsemi.com 8 table 9. screening no. test condition number of devices test method test 8 temperature cycling mil-std-883 method 1010 all b - 10 cycles ?55 c +125 c 9 biased burn-in mil-std-883 method 1015 all 240 h at +125 c 10 mobile particle detection mil-std-883 method 2020 all a 11 fine leak test mil-std-883 method 1014 all a 12 gross leak test mil-std-883 method 1014 all c 13 hcrt electrical measurements 12mbe83443f all ht +85 c lt ?40 c rt +22 c 14 final visual inspection 12mon56972e all figure 2. has2 assembly lat flow
NOIH2SM1000A www.onsemi.com 9 tables and figures specification tables table 10. type variant summary has2 type variants engineering model flight model optical quality (see optical quality ? definitions on page 66) dead pixels 100 20 bright pixels in fpn image 50 20 bad pixels in prnu image 150 50 bad columns 5 0 bad rows 5 0 bright pixel clusters 2 adjacent bright pixels 25 2 4 or more adjacent bright pixels 10 0 dsnu defects at 22 dec bol 1200 1000 dsnu defects at 22 dec eol 1500 1250 particle contamination fixed particles outside focal plane n/a n/a mobile particles > 20 m 0 0 fixed particles on focal plane > 20 m 0 0 mobile particles > 10 m and < 20 m 20 10 fixed particles on focal plane > 10 m and < 20 m particles < 10 m n/a n/a wafer lot acceptance (see section wafer lot acceptance on page 6) no yes glass lot acceptance (see section glass lot acceptance on page 6) no yes assembly lot acceptance (table 7 on page 6) no yes periodic testing (table 8 on page 7) no yes screening (table 9 on page 7) no yes calibration data no yes visual inspection + particle mapping no yes table 11. maximum ratings no. characteristic min typ max unit remarks 1 any supply voltage except vdd_res ?0.5 3.3 +7.0 v 2 supply voltage at vdd_res ?0.5 3.3 +5.0 v 3.3 v for normal operation; up to 5 v for increased full well capacity. 3 voltage on any input terminal ?0.5 3.3 vdd + 0.5 v 4 soldering temperature na na 260 c hand soldering only; see solder- ing instructions on page 1 5 operating temperature ?40 na +85 c 6 storage temperature ?55 na +125 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
NOIH2SM1000A www.onsemi.com 10 detailed specifications ? all type variants table 12. general specifications no. characteristic min typ max unit remarks 1 image sensor format n/a 1024 x 1024 n/a pixels 2 pixel size n/a 18 n/a m 3 adc resolution n/a 12 n/a bit 10-bit accuracy at 5 msamples/sec table 13. silicon particle contamination specifications no. characteristic min typ max unit remarks 1 optical quality: particle max size n/a n/a 20 m see type variant summary on page 9 table 14. mechanical specifications parameter description min typ max units die (refer to figure 3 ?die placement? on page 10) flatness of image area (note 1) na 7.4 na m flatness of glass lid (note 2) na 90 150 m mass 7.7 7.85 8.0 g die thickness ( ? 10) 740 (10) m die center, x offset to the center of package (a) ( ? 50) 0 (+50) m die center, y offset to the center of the package (a) ( ? 50) 0 (+50) m die position, x tilt ? 0.3 0 0.3 deg die position, y tilt ? 0.3 0 0.3 deg die placement accuracy in package ( ? 50) (+50) m die rotation accuracy ? 0.4 0.4 deg optical center referenced from package center (x-dir) (b) ( ? 50) +571 (+50) m optical center referenced from package center (y-dir) (b) ( ? 50) +109.5 (+50) m distance from top of the die surface to top of the glass lid ( ? 0.31) 1.78 (0.31) mm total thickness refer to package diagram (figure 4 on page 24) 1. peak-to-peak at 22 3 c. specified by the foundry over an entire 8-inch wafer. 2. towards ceramic package. figure 3. die placement a: package center/die center b: optical center y x pin 1
NOIH2SM1000A www.onsemi.com 11 table 15. glass lid specifications no. characteristic min typ max unit remarks 1a xy size 26.7 x 26.7 26.8 x 26.8 26.9 x 26.9 mm 1b thickness 1.4 1.5 1.6 mm 2a spectral range for optical coating of window 440 na 1100 nm 2b reflection coefficient for window na <0.8 <1.3 % over bandwidth indicated in 2a 3 optical quality: scratch max width scratch max number dig max size dig max number n/a n/a 10 5 60 25 m table 16. environmental specifications no. characteristic min typ max unit remarks 1 operating temperature ?40 na +85 c 2 storage temperature ?55 na +125 c lower storage temperatures (up to ?80 c) have been tested and the device survives, but this is not a fully qualified temperature. 3 sensor total dose radiation tolerance n/a 42 n/a krad (si) tested for functionality up to 300 krad, 42 krad is guaranteed 4 sensor sel threshold with adc enabled na na >110 mev cm 3 mg -1 equivalent let value table 17. electrical specifications no characteristic min typ max unit remarks 1 total power supply current stand-by 15 19 23 ma 2 total power supply current, operational 24 28.5 33.5 ma adc at 5 mhz sampling rate measured 3 power supply current to adc, operational: analog + digital 17 19 21 ma adc at 5 mhz sampling rate measured 4 power supply current to image core, operational 14 15.5 17 ma 5 input impedance digital input 3 na na m 6 input impedance adc input 3 na na m 7 output amplifier voltage range 2.2 2.45 2.6 v 8 output amplifier gain setting 0 na 1 na ? nominal 1 measured reference 9 output amplifier gain setting 1 1.9 2.1 2.3 ? nominal 2 relative to setting 0 10 output amplifier gain setting 2 3.8 4.1 4.4 ? nominal 4 relative to setting 0 11 output amplifier gain setting 3 7.2 7.7 8.2 ? nominal 8 relative to setting 0 12 output amplifier offset setting 0 0.9 0.95 1.0 v 0 decodes to middle value 13 output amplifier offset setting 31 1.31 1.36 1.41 v 14 output amplifier offset setting 32 0.5 0.56 0.62 v 15 output amplifier offset setting 63 0.88 0.93 0.98 v 16 adc ladder network resistance na 1.8 na k typical value
NOIH2SM1000A www.onsemi.com 12 table 17. electrical specifications no remarks unit max typ min characteristic 17 adc differential nonlinearity na 7 11 lsb 18 adc integral nonlinearity na 8 18 lsb 19 adc setup time 5 na na ns analog_in stable to clk_adc ris- ing 20 adc hold time 10 na na ns analog_in stable after clk_adc rising edge 21 adc delay time na na 20 ns 22 adc latency na 6.5 na - cycles of clk_adc 23 adc ideal input range 0.85 na 2.0 v vlow_adc to vhigh_adc 24 saturation voltage output swing 1.20 1.49 na v vdd_res = 3.3 v 25 output range 0.8 na 2.1 v measured with pga in unity gain, offset = 0.8 v, low is dark, high is bright. 26 linear range of pixel signal swing 40 50 0.75 na ke- v measured within 1% 27 linear range 60 82 na ke- measured within 5% 28 full well charge 90 100 na ke- measured with vdd_res = 3.3 v 29 quantum efficiency x fillfactor na 45 na % measured between 500 nm and 650 nm. refer to section spectral response on page 26 for complete curve. 30 spectral response na 33.3 na % measured average over 400 nm ? 900 nm. 31 charge to voltage conversion factor na 16.9 na v/e- at pixel 32 charge to voltage conversion factor 13 14.8 15.6 v/e- measured at output signal_out, unity gain 33a temporal noise (soft reset) na 55 95 e- dark noise, with dr/ds, internal adc 33b temporal noise (hard reset) n/a 75 125 e- dark noise, with dr/ds, internal adc 33c temporal noise (hts reset) na 65 110 e- dark noise, with dr/ds, internal adc 34a temporal noise (ndr soft reset) na 75 100 e- 34b temporal noise (ndr hard reset) na 75 100 e- 34c temporal noise (ndr hts reset) na 70 100 e- 35 adc quantization noise na 7 na e- 36a local fixed pattern noise standard deviation (hard reset) na 110 160 e- with dr/ds 36b local fixed pattern noise standard deviation (soft reset) na 70 140 e- with dr/ds 36c local fixed pattern noise standard deviation (hts reset) na 95 140 e- with dr/ds 37a global fixed pattern noise standard deviation (hard reset) na 115 180 e- with dr/ds 37b global fixed pattern noise standard deviation (soft reset) na 90 140 e- with dr/ds 37c global fixed pattern noise standard deviation (hts reset) na 110 180 e- with dr/ds
NOIH2SM1000A www.onsemi.com 13 table 17. electrical specifications no remarks unit max typ min characteristic 37d global fixed pattern noise standard deviation (ndr, soft reset) 14 15 18 e- with ndr/cds and external adc 37e local column fixed pattern noise standard deviation (ndr, soft reset) 14 15 18 e- with ndr/cds and external adc 38 average dark signal na 190 400 e-/s at 22 2 c die temp, bol see ?dark current vs temperature model? on page 30 39 average dark signal na 5550 8730 e-/s at 22 2 c die temp, eol (25 krad) 40 dark signal temperature dependency 5 5.8 8 c sensor temperature increase for doubled average dark current. 41 local dark signal non-uniformity standard deviation na 260 400 e-/s at 22 2 c die temp, bol 96% of bol average 42 global dark signal non-uniformity standard deviation n/a 275 500 e-/s at 22 2 c die temp, bol 96% of bol average 43 local photo response non-uniformity, standard deviation na 0.8 1.0 % of average response 44 global photo response non-uniformity, standard deviation na 1.8 5 % of average response 45 mtf x direction na 0.35 na na at nyquist measured 46 mtf y direction na 0.35 na - at nyquist measured 47 pixel to pixel crosstalk x direction na 9.8 na % of total source signal ? see ?pixel ? to ? pixel cross talk? on page 34 for 2 ? d plot 48 pixel to pixel crosstalk y direction na 9.8 na % of total source signal ? see ?pixel ? to ? pixel cross talk? on page 34 for 2 ? d plot 49 anti-blooming capability 200 1000 na typical 50 pixel rate na 5 10 mhz 51 temperature sensor transfer curve na ?4.64 na mv/ c bol 52 temperature sensor output signal range, min to max (typical) 800 na 1700 mv bol 53 temperature sensor linearity na 3 na mv bol 54 temperature sensor transfer curve na ?4.64 na mv/ c eol 55 temperature sensor output signal range, min to max (typical) 800 na 1700 na eol the following formulas are applicable to convert % vsat and mv/s into e- and e-/s: other definitions ? conversion gain for has: 14.8 v/e- ? definition for local measurements: 32 x 32 pixels ? definition for global measurements: full pixel array
NOIH2SM1000A www.onsemi.com 14 table 18. electrical and electro-optical measurements at room temperature 22 c no. characteristic min typ max unit remarks 1 total power supply current stand-by 15 19 23 ma 2 total power supply current, operational 24 28.5 33.5 ma adc at 5 mhz sampling rate 3 power supply current to adc, operational 17 19 21 ma adc at 5 mhz sampling rate 4 power supply current to image core, operational 14 15.5 17 ma 5 input impedance digital input 3 na na m 6 input impedance adc input 3 na na m 7 output impedance digital outputs na na 400 w 8 output impedance analog output na na 1 k 9 output amplifier voltage range 2.2 2.45 2.6 v 10 output amplifier gain setting 0 na 1 na - nominal 1 measured reference 11 output amplifier gain setting 1 1.9 2.1 2.3 - nominal 2 relative to setting 0 12 output amplifier gain setting 2 3.8 4.1 4.4 - nominal 4 relative to setting 0 13 output amplifier gain setting 3 7.2 7.7 8.2 - nominal 8 relative to setting 0 14 output amplifier offset setting 0 0.9 0.95 1.0 v 0 decodes to middle value 15 output amplifier offset setting 31 1.31 1.36 1.41 v 16 output amplifier offset setting 32 0.5 0.56 0.62 v 17 output amplifier offset setting 63 0.88 0.93 0.98 v 18 adc differential nonlinearity n/a 7 11 lsb 19 adc integral nonlinearity n/a 8 18 lsb 20 saturation voltage output swing 1.20 1.49 na v vdd_res = 3.3 v 21 output range 0.8 na 2.1 v pga in unity gain, offset = 0.8 v, low is dark, high is bright. 22a temporal noise (soft reset) na 55 95 e- dark noise, with dr/ds, internal adc 22b temporal noise (hard reset) na 75 125 e- dark noise, with dr/ds, internal adc 22c temporal noise (hts reset) na 65 110 e- dark noise, with dr/ds, internal adc 23a temporal noise (ndr soft reset) na 75 100 e- 23b temporal noise (ndr hard reset) na 75 100 e- 23c temporal noise (ndr hts reset) na 70 100 e- 24 adc quantization noise na 7 na e- 25a local fixed pattern noise standard deviation (soft reset) n/a 70 140 e- with dr/ds 25b local fixed pattern noise standard deviation (hard reset) na 110 160 e- with dr/ds 25c local fixed pattern noise standard deviation (hts reset) na 95 140 e- with dr/ds 26a global fixed pattern noise standard deviation (soft reset) na 90 140 e- with dr/ds
NOIH2SM1000A www.onsemi.com 15 table 18. electrical and electro-optical measurements at room temperature 22 c no. remarks unit max typ min characteristic 26b global fixed pattern noise standard deviation (hard reset) na 115 180 e- with dr/ds 26c global fixed pattern noise standard deviation (hts reset) na 110 180 e- with dr/ds 27 average dark signal na 190 400 e-/s at 22 2 c die temp 28 local dark signal non-uniformity standard deviation na 260 400 e-/s at 22 2 c 29 global dark signal non-uniformity standard deviation na 275 500 e-/s at 22 2 c 30 local photo response non-uniformity, standard deviation na 0.8 1.0 % of average response 31 global photo response non-uniformity, standard deviation na 1.8 5 % of average response table 19. electrical and electro-optical measurements at high temperature +85 c no. characteristic min typ max unit remarks 1 total power supply current stand-by 15 19 23 ma 2 total power supply current, operational 24 28.5 33.5 ma adc at 5 mhz sampling rate 3 power supply current to adc, operational 17 19 21 ma adc at 5 mhz sampling rate 4 power supply current to image core, operational 14 15.5 17 ma 5 input impedance digital input 3 na na m 6 input impedance adc input 3 na na m 7 output impedance digital outputs na na 400 w 8 output impedance analog output na na 1 k 9 output amplifier voltage range 2.2 2.45 2.6 v 10 output amplifier gain setting 0 na 1 na - nominal 1 measured reference 11 output amplifier gain setting 1 1.9 2.1 2.3 - nominal 2 relative to setting 0 12 output amplifier gain setting 2 3.7 4.0 4.3 - nominal 4 relative to setting 0 13 output amplifier gain setting 3 7.0 7.5 8.0 - nominal 8 relative to setting 0 14 output amplifier offset setting 0 0.91 0.97 1.03 v 0 decodes to middle value 15 output amplifier offset setting 31 1.33 1.38 1.43 v 16 output amplifier offset setting 32 0.52 0.59 0.66 v 17 output amplifier offset setting 63 0.91 0.96 1.01 v 18 adc differential nonlinearity na 8 11 lsb 19 adc integral nonlinearity na 10 18 lsb 20 saturation voltage output swing 1.20 1.52 na v vdd_res = 3.3 v 21 output range 0.8 na 2.1 v pga in unity gain, offset = 0.8 v, low is dark, high is bright. 22a temporal noise (soft reset) na 66 110 e- dr/ds 22b temporal noise (hard reset) na 85 125 e- dr/ds 22c temporal noise (hts reset) na 73 110 e- dr/ds
NOIH2SM1000A www.onsemi.com 16 table 19. electrical and electro-optical measurements at high temperature +85 c no. remarks unit max typ min characteristic 23a temporal noise (ndr soft reset) na 200 400 e- 23b temporal noise (ndr hard reset) na 170 300 e- 23c temporal noise (ndr hts reset) na 65 125 e- 24 adc quantization noise na 7 na e- 25a local fixed pattern noise standard deviation (soft reset) na 82 160 e- with dr/ds 25b local fixed pattern noise standard deviation (hard reset) na 95 160 e- with dr/ds 25c local fixed pattern noise standard deviation (hts reset) na 100 160 e- with dr/ds 26a global fixed pattern noise standard devi- ation (soft reset) na 80 140 e- with dr/ds 26b global fixed pattern noise standard devi- ation (hard reset) na 97 160 e- with dr/ds 26c global fixed pattern noise standard devi- ation (hts reset) na 115 300 e- with dr/ds 27 local photo response non-uniformity, stan- dard deviation na 0.74 1.0 % of average response 28 global photo response non-uniformity, standard deviation na 1.7 5 % of average response table 20. electrical and electro-optical measurements at low temperature ?40 c no. characteristic min typ max unit remarks 1 total power supply current stand-by 15 19 23 ma 2 total power supply current, operational 24 28.5 33.5 ma adc at 5 mhz sampling rate 3 power supply current to adc, operational 17 19 21 ma adc at 5 mhz sampling rate 4 power supply current to image core, operational 14 15.5 17 ma 5 input impedance digital input 3 na na m 6 input impedance adc input 3 na na m 7 output impedance digital outputs na na 400 w 8 output impedance analog output na na 1 k 9 output amplifier voltage range 2.2 2.45 2.6 v 10 output amplifier gain setting 0 na 1 na - nominal 1 measured reference 11 output amplifier gain setting 1 1.9 2.1 2.3 - nominal 2 relative to setting 0 12 output amplifier gain setting 2 3.8 4.1 4.4 - nominal 4 relative to setting 0 13 output amplifier gain setting 3 7.2 7.7 8.2 - nominal 8 relative to setting 0 14 output amplifier offset setting 0 0.89 0.94 0.99 v 0 decodes to middle value 15 output amplifier offset setting 31 1.30 1.35 1.40 v 16 output amplifier offset setting 32 0.46 0.53 0.6 v 17 output amplifier offset setting 63 0.86 0.92 0.98 v 18 adc differential nonlinearity n/a 7 11 lsb
NOIH2SM1000A www.onsemi.com 17 table 20. electrical and electro-optical measurements at low temperature ?40 c no. remarks unit max typ min characteristic 19 adc integral nonlinearity n/a 11 18 lsb 20 saturation voltage output swing 1.20 1.49 na v vdd_res = 3.3 v 21 output range 0.8 na 2.1 v pga in unity gain, offset = 0.8 v, low is dark, high is bright. 22a temporal noise (soft reset) na 59 100 e- dr/ds 22b temporal noise (hard reset) na 77 125 e- dr/ds 22c temporal noise (hts reset) na 70 125 e- dr/ds 23a temporal noise (ndr soft reset) na 80 125 e- 23b temporal noise (ndr hard reset) na 80 125 e- 23c temporal noise (ndr hts reset) na 75 125 e- 24 adc quantization noise na 7 na e- 25a local fixed pattern noise standard deviation (soft reset) na 70 140 e- with dr/ds 25b local fixed pattern noise standard deviation (hard reset) na 90 140 e- with dr/ds 25c local fixed pattern noise standard deviation (hts reset) na 100 160 e- with dr/ds 26a global fixed pattern noise standard deviation (soft reset) na 70 140 e- with dr/ds 26b global fixed pattern noise standard deviation (hard reset) na 95 140 e- with dr/ds 26c global fixed pattern noise standard deviation (hts reset) na 120 180 e- with dr/ds 27 local photo response non-uniformity, stan- dard deviation na 0.8 1.0 % of average response measured 28 global photo response non-uniformity, standard deviation na 1.8 5 % of average response measured table 21. drift limits electrical and electro-optical measurements at room temperature +22 c characteristic min target max units total power supply current, operational ? 7 0 7 ma total power supply current stand-by ? 6.4 0 6.4 ma adc differential nonlinearity ? 1.1 0 1.1 lsb average dark signal ? 200 ? 10 180 e-/s global dark signal non-uniformity standard deviation ? 230 3 230 e-/s output amplifier offset setting 0 ? 100 2.2 100 mv
NOIH2SM1000A www.onsemi.com 18 table 22. parameter drift values for radiation testing electrical and electro-optical measurements at room temperature +22 c no. characteristic typical value max drift unit remarks 1 total power supply current stand-by 18.5 2 ma 2 total power supply current, operational 29 3 ma adc at 5 mhz sampling rate 3 power supply current to adc, operational 19 2 ma adc at 5 mhz sampling rate 4 power supply current to image core, opera- tional 15.5 2 ma 5 output impedance digital outputs n/a 20 w 6 output impedance analog output n/a 20 w 7 output amplifier voltage range 2.45 0.2 v 8 output amplifier gain setting 0 1 n/a - nominal 1 measured reference 9 output amplifier gain setting 1 2.1 0.2 - nominal 2 relative to setting 0 10 output amplifier gain setting 2 4.1 0.3 - nominal 4 relative to setting 0 11 output amplifier gain setting 3 7.7 0.5 - nominal 8 relative to setting 0 12 output amplifier offset setting 0 0.95 0.1 v 0 decodes to middle value 13 output amplifier offset setting 31 1.36 0.1 v 14 output amplifier offset setting 32 0.56 0.1 v 15 output amplifier offset setting 63 0.93 0.1 v 16 adc differential nonlinearity 7 1 lsb 17 adc integral nonlinearity 8 1 lsb 18 saturation voltage output swing 1.49 0.2 v vdd_res = 3.3 v 19 output range n/a 0.2 v pga in unity gain, offset = 0.8 v, low is dark, high is bright. 20a temporal noise (soft reset) 55 +30 e- dark noise, with dr/ds, internal adc 20b temporal noise (hard reset) 75 +30 e- dark noise, with dr/ds, internal adc 20c temporal noise (hts reset) 65 +30 e- dark noise, with dr/ds, internal adc 21a temporal noise (ndr soft reset) 75 +40 e- 21b temporal noise (ndr hard reset) 75 +40 e- 21c temporal noise (ndr hts reset) 70 +40 e- 22 adc quantization noise 7 na e- 23a local fixed pattern noise standard deviation (soft reset) 70 +200 e- with dr/ds 23b local fixed pattern noise standard deviation (hard reset) 110 +100 e- with dr/ds 23c local fixed pattern noise standard deviation (hts reset) 95 +100 e- with dr/ds 24a global fixed pattern noise standard deviation (soft reset) 90 +200 e- with dr/ds 24b global fixed pattern noise standard deviation (hard reset) 115 +100 e- with dr/ds 24c global fixed pattern noise standard deviation (hts reset) 110 +100 e- with dr/ds 25 average dark signal 190 +6000 e-/s at 22 2 c die temp
NOIH2SM1000A www.onsemi.com 19 table 22. parameter drift values for radiation testing electrical and electro-optical measurements at room temperature +22 c no. remarks unit max drift typical value characteristic 26 local dark signal non-uniformity standard deviation 260 +1500 e-/s at 22 2 c 27 global dark signal non-uniformity standard deviation 275 +1500 e-/s at 22 2 c 28 local photo response non-uniformity, stand- ard deviation 0.8 +0.1 % of average response 29 global photo response non-uniformity, stan- dard deviation 1.8 +0.3 % of average response table 23. conditions for high temperature reverse bias burn ? in no. characteristics symbol test condition unit not applicable table 24. conditions for power burn ? in and operating life tests no. characteristics symbol test condition unit 1 ambient temperature tamb 125 c 2 all power supplies vdd 3.3 v 3 bias conditions see figures 49, 50, 51 , 52 on page 58 4 clock frequency 10 mhz
NOIH2SM1000A www.onsemi.com 20 table 25. electrical and electro-optical measurements on completion of environmental tests and at intermediate points and on completion of endurance testing electrical and electro-optical measurements at room temperature +22 c no. characteristic min typ max unit remarks 1 total power supply current stand-by 15 19 23 ma 2 total power supply current, operational 24 28.5 33.5 ma adc at 5 mhz sampling rate measured 3 power supply current to adc, operational 17 19 21 ma at 5 mhz 4 power supply current to image core, operational 14 15.5 17 ma 5 input impedance digital input 3 na na m 6 input impedance adc input 3 na na m 7 output impedance digital outputs na na 400 w 8 output impedance analog output na na 1 k 9 output amplifier voltage range 2.2 2.45 2.6 v 10 output amplifier gain setting 0 na 1 na - nominal 1 measured reference 11 output amplifier gain setting 1 1.9 2.1 2.3 - nominal 2 relative to setting 0 12 output amplifier gain setting 2 3.8 4.1 4.4 - nominal 4 relative to setting 0 13 output amplifier gain setting 3 7.2 7.7 8.2 - nominal 8 relative to setting 0 14 output amplifier offset setting 0 0.90 0.95 1.0 v 0 decodes to middle value 15 output amplifier offset setting 31 1.31 1.36 1.41 v 16 output amplifier offset setting 32 0.50 0.56 0.62 v 17 output amplifier offset setting 63 0.88 0.93 0.98 v 18 adc differential nonlinearity na 7 11 lsb 19 adc integral nonlinearity na 8 18 lsb 20 saturation voltage output swing 1.20 1.49 n/a v vdd_res = 3.3 v 21 output range 0.8 na 2.1 v pga in unity gain, offset = 0.8 v, low is dark, high is bright. 22a temporal noise (soft reset) na 55 95 e- dark noise, with dr/ds, internal adc 22b temporal noise (hard reset) na 75 125 e- dark noise, with dr/ds, internal adc 22c temporal noise (hts reset) na 65 110 e- dark noise, with dr/ds, internal adc 23a temporal noise (ndr soft reset) na 75 100 e- 23b temporal noise (ndr hard reset) na 75 100 e- 23c temporal noise (ndr hts reset) na 70 100 e- 24 adc quantization noise na 7 na e- 25a local fixed pattern noise standard deviation (soft reset) na 70 140 e- with dr/ds 25b local fixed pattern noise standard deviation (hard reset) na 110 160 e- with dr/ds 25c local fixed pattern noise standard deviation (hts reset) na 95 140 e- with dr/ds
NOIH2SM1000A www.onsemi.com 21 table 25. electrical and electro-optical measurements on completion of environmental tests and at intermediate points and on completion of endurance testing electrical and electro-optical measurements at room temperature +22 c no. remarks unit max typ min characteristic 26a global fixed pattern noise standard deviation (soft reset) na 90 140 e- with dr/ds 26b global fixed pattern noise standard deviation (hard reset) na 115 180 e- with dr/ds 26c global fixed pattern noise standard deviation (hts reset) na 110 180 e- with dr/ds 27 average dark signal na 190 400 e-/s at 22 2 c die temp 28 local dark signal non-uniformity standard deviation na 260 400 e-/s at 22 2 c 29 global dark signal non-uniformity standard deviation na 275 500 e-/s at 22 2 c 30 local photo response non-uniformity, stand- ard deviation na 0.8 1.0 % of average response 31 global photo response non-uniformity, stan- dard deviation na 1.8 5 % of average response table 26. electrical and electro-optical measurements during and on completion of total-dose irradiation testing (50krad) electrical and electro-optical measurements at room temperature +22 c no. characteristic symbol min typ max unit remarks 1 total power supply current stand-by 15 19 23 ma 2 total power supply current, operational 24 28.5 33.5 ma 3 power supply current to adc, operational 17 19 21 ma adc at 5 mhz sampling rate 4 power supply current to image core, opera- tional 14 15.5 17 ma 5 output impedance digital outputs na na 400 w 6 output impedance analog output na na 1 k 7 output amplifier voltage range 2.2 2.45 2.6 v 8 output amplifier gain setting 0 na 1 na - nominal 1 measured reference 9 output amplifier gain setting 1 1.9 2.1 2.3 - nominal 2 relative to setting 0 10 output amplifier gain setting 2 3.8 4.1 4.4 - nominal 4 relative to setting 0 11 output amplifier gain setting 3 7.2 7.7 8.2 - nominal 8 relative to setting 0 12 output amplifier offset setting 0 0.90 0.95 1.0 v 0 decodes to middle value 13 output amplifier offset setting 31 1.31 1.36 1.41 v 14 output amplifier offset setting 32 0.50 0.56 0.62 v 15 output amplifier offset setting 63 0.88 0.93 0.98 v 16 adc differential nonlinearity n/a 8 11 lsb 17 adc integral nonlinearity n/a 9 18 lsb 18 saturation voltage output swing 1.20 1.49 n/a v vdd_res = 3.3 v 19 output range 0.8 n/a 2.1 v pga in unity gain, offset = 0.8 v, low is dark, high is bright.
NOIH2SM1000A www.onsemi.com 22 table 26. electrical and electro-optical measurements during and on completion of total-dose irradiation testing (50krad) electrical and electro-optical measurements at room temperature +22 c no. remarks unit max typ min characteristic symbol 20 temporal noise (soft reset) na 55 95 e- dark noise, with dr/ds, internal adc 21 temporal noise (hard reset) na 75 125 e- dark noise, with dr/ds, internal adc 22a temporal noise (hts reset) na 65 110 e- dark noise, with dr/ds, internal adc 22b temporal noise (ndr soft reset) na 75 100 e- 22c temporal noise (ndr hard reset) na 75 100 e- 23a temporal noise (ndr hts reset) na 70 100 e- 23b adc quantization noise na 7 na e- 23c local fixed pattern noise standard devi- ation (soft reset) na 70 350 e- with dr/ds 24 local fixed pattern noise standard devi- ation (hard reset) na 110 160 e- with dr/ds 25a local fixed pattern noise standard devi- ation (hts reset) na 95 200 e- with dr/ds 25b global fixed pattern noise standard devi- ation (soft reset) na 90 350 e- with dr/ds 25c global fixed pattern noise standard devi- ation (hard reset) na 115 180 e- with dr/ds 26a global fixed pattern noise standard devi- ation (hts reset) na 110 200 e- with dr/ds 26b average dark signal na 5550 8730 e-/s at 22 2 c die temp 26c local dark signal non-uniformity standard deviation na 260 2000 e-/s at 22 2 c 27 global dark signal non-uniformity standard deviation na 275 2000 e-/s at 22 2 c 28 local photo response non-uniformity, stan- dard deviation na 0.8 1.0 % of average response 29 global photo response non-uniformity, standard deviation na 1.8 5 % of average response
NOIH2SM1000A www.onsemi.com 23 table 27. electro ? optical measurements on the optical bench no. characteristic symbol min typ max unit remarks 1 linear range of pixel signal swing 40 50 0.75 na ke- v measured within 1% 2 linear range 60 82 na ke- measured within 5% 3 full well charge 90 100 na ke- measured vdd_res = 3.3 v 4 quantum efficiency x fillfactor na 45 na % measured between 500 nm and 650 nm. see specification figures on page 24 for complete curve 5 spectral response na 33.3 - % measured average over 400 nm ? 900 nm. 6 charge to voltage conversion factor na 16.9 - v/e- at pixel 7 charge to voltage conversion factor 13 14.8 15.6 v/e- measured at output signal_out, unity gain 8 mtf x direction na 0.35 na - at nyquist measured 9 mtf y direction na 0.35 na - at nyquist measured 10 pixel to pixel crosstalk x direction na 9.8 na % of total source signal ? see spe- cification figures on page 24 for 2 ? d plot 11 pixel to pixel crosstalk y direction na 9.8 na % of total source signal ? see spe- cification figures on page 24 for 2 ? d plot 12 anti-blooming capability na 1000 na ke- predicted value table 28. typical power supply settings and sensor settings power supply settings adc_vlow 0.85 v adc_vhigh 2.0 v v_adc_digital 3.3 v v_adc_analog 3.3 v vddd 3.3 v vdda 3.3 v vres 3.3 v for sr / 4.2 v for hr vpix 3.3 v (for hts switched to 0.75 v) sensor settings read out modes destructive ? nondestructive integration time 195 s gain setting unity offset setting 0 x clock period 100 ns
NOIH2SM1000A www.onsemi.com 24 specification figures jldcc84 case 114ak issue a figure 4. 84 ? pin jlcc package diagram
NOIH2SM1000A www.onsemi.com 25 figure 5. glass lid dimensions figure 6. has2 package photo
NOIH2SM1000A www.onsemi.com 26 response curves spectral response figure 7. measured spectral response of has rad ? hard pixel (black curve indicates average spectral response 0 0.05 0.1 0.15 0.2 0.25 0.3 400 10 % 20 % 30 % 40 % 50 % 60 % 500 600 700 800 900 1000 spectral response [a/w] wavelength [nm] figure 8. average measured spectral response of has rad ? hard pixel recalculated to qexff 0 5 10 15 20 25 30 35 40 45 50 400 wa vel e n gth [nm] qe x ff [%] measured average curve smoothed trend 500 600 700 800 900 1000
NOIH2SM1000A www.onsemi.com 27 photo ? response curve figure 9. pixel response curve: photo ? electrons versus signal voltage 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 number of electrons output vol tage [v] pix 1 pix 2 pix 3 pix 4 20000 40000 60000 80000 100000 120000 140000 fit to the linear response curve with the same conversion gain (solid black line). the dashed lines indicate linear response curves with ?5% and +5% conversion gain. a detailed analysis is performed in the range < 4000 e-. the dashed lines corresponds to soft reset. the others to hard reset. figure 10. pixel response curve < 4000 e ?
NOIH2SM1000A www.onsemi.com 28 0 0.5 1 1.5 2 0 number of elect rons [e ? ] out put voltage [ v] gain 1 (1) gain 2 (2.27) gain 4 (4.54) gain 8 (8.55) figure 11. measured response curves of two pixels on two devices at different gain setting 20000 40000 60000 80000 100000 120000 table 29. overview of the offset at different gain settings device 1 6 average average gain setting offset [v] [v] [v] offset drift [mv] 1 offset_g1 0.86 0.85 0.86 0 2 offset_g2 0.93 0.91 0.92 65 4 offset_g4 1.02 0.99 1.00 149 8 offset_g8 1.18 1.14 1.16 303 fixed pattern noise figure 12 shows a log linear plot of the fixed pattern noise in destructive readout before and after radiation. figure 12. typical fpn histogram in dr before and after tid fpn dr histogram tid 1 10 10 0 1000 1000 0 100000 100 2^12 [ d n] # pixels bol 4krad tid 13krad tid 20krad tid 41krad tid 150 200 250 300 350 400
NOIH2SM1000A www.onsemi.com 29 figure 13 shows a log linear plot of the fixed pattern noise in destructive readout before and after a 2000 h life test, which can be considered as eol 41 behavior. figure 13. fpn histogram in dr before and after 2000 h life test dr histogram bol - eol 1 10 100 100 0 10000 100000 200 2^12 [dn ] # pixels bol eol 220 240 260 280 300 320 340 figure 14 shows a log linear plot of the fixed pattern noise in nondestructive readout before and after a 2000 h life test, which can be considered as eol 42 behavior. figure 14. fpn histogram in ndr before and after 2000 h life test ndr reset level histogram b ol ? eol 1 10 10 0 1000 10000 100000 0 2^ 12 [ d n] # pixels bol eol 100 200 300 400 500 600 700 800 900 1000
NOIH2SM1000A www.onsemi.com 30 dark current vs. temperature model figure 15. temperature dependence of the dark current (in e/s) measured on a sample y = 16.336e 0.1082x r 2 = 0.9995 0.1 1 10 100 1000 10000 100000 1000000 -60?-40?-20020?406080?100 t emp er atu r e [d eg c] aver ag e d ark current [e ? /s] theoretical curve following model is consistent with what has been measured for typical values: with dc the dark current in e/s dc 0 the dark current at 30 c and 0 krad = 300 e/s tid the total ionizing dose (in krad(si)) t the temperature (in c) a dc the slope of the curve at 30 c = 325 e/s/krad(si) tdc,d1 = 5.8 c and tdc,d2 = 7.1 c dcnu0 the dark current non-uniformity at 30 c and 0 krad = 230 e/s a dcnu the slope of the curve at 30 c = 33.6 e/s/krad(si) tdcnu,d1 = 9.5 c and tdcnu,d2 = 9.5 c t0 = 30 c following model is consistent with what has been measured for worst case values: with dc the dark current in e/s dc 0 the dark current at 30 c and 0 krad = 550 e/s tid the total ionizing dose (in krad(si)) t the temperature (in c) a dc the slope of the curve at 30 c = 480 e/s/krad(si) tdc,d1,l = 6.6 c and tdc,d2,l = 8 c for t < t0 tdc,d1,h = 5 c and tdc,d2,h = 6.5 c for t > t0 dcnu0 the dark current non-uniformity at 30 c and 0 krad = 400 e/s a dcnu the slope of the curve at 30 c = 45 e/s/krad(si) tdcnu,d1,l = 10.5 c and tdcnu,d2,l = 10.5 c for t < t0 tdcnu,d1,h = 8.5 c and tdcnu,d2,h = 8.5 c for t > t0 t0 = 30 c
NOIH2SM1000A www.onsemi.com 31 dcnu distributions figure 16 and figure 17 show the distributions of the dark current in mv/s and e/s respectively for a number of devices and the average distribution. figure 16. dark current distribution (in mv/s) at 25 c ambient temperature 0.001 0.01 0.1 1 10 100 1000 10000 020?40?60?80100120140160180200 dark current [mv/s] relative frequency ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average figure 17. dark current distribution (in e/s) at 25 c ambient temperature 0.001 0.01 0.1 1 10 100 1000 10000 0200040006000800010000?12000 dark cu rren t [e/s] relative frequency ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average
NOIH2SM1000A www.onsemi.com 32 figure 18 and figure 19 show the cumulative distributions of the dark current in mv/s and e/s respectively for a number of devices and the average cumulative distribution. figure 18. cumulative dark current distribution (in mv/s) at 25 c ambient temperature 0.0001 0.001 0.01 0.1 1 10 100 0?20406080100?120?140?160?180?200 dark current [mv/s] ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average c umu la ti ve fr e que ncy figure 19. cumulative dark current distribution (in e/s) at 25 c ambient temperature 0.0001 0.001 0.01 0.1 1 10 100 0200040006000800010000?12000 dark current [e/s] cumulative frequency ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average
NOIH2SM1000A www.onsemi.com 33 figure 20 shows the percentage of pixels versus their normalized dark current for the measurement and for a gaussian distribution with the same average value and standard deviation. in the measured distribution, about 1.1?1.2% of the pixels exhibit a dark current that exceeds the 3 limit that is typically used to exclude pixels from the measurements (about 10 times larger than for gaussian distribution) figure 20. comparison between measured distribution and gaussian distribution 0.0001 0.001 0.01 0.1 1 10 100 0 (dark cur rent ? average dark curr ent ) / (s t. dev. dark curre nt ) per centage of pixels [%] measurement gaussian distribution 123 4 56 78 910 figure 21 shows the dsnu distributions during tid irradiation figure 21. dsnu distributions during tid irradiation dsnu distribution during total dose irra diation an d after annealing 1 10 100 1000 10000 0 pre rad 4 krad 14 krad 20 krad 41 krad 168 h ht annealing 3 mnth rt annealing biased conditions 500 1000 1500 2000 2500 3000 3500 4000 4500 number of pixels adu value [0 ? 2^12]
NOIH2SM1000A www.onsemi.com 34 temperature sensor figure 22. temperature sensor voltage sensitivity (the solid line indicates a linear fit with 1.38 v as output voltage at 30 c and a slope of ? 4.64 mv/ c) 1.2 1.22 1.24 1.26 1.28 1.3 1.32 1.34 1.36 1.38 1.4 30 tempe rature [c] output volta ge [v] -5 -4 -3 -2 -1 0 1 2 3 4 5 d eviati o n fro m fi tted cu rve [mv] measurement points fitted curve deviation 35 40 45 50 55 60 65 70 75 pixel ? to ? pixel cr osstalk figure 23. cross talk with central pixel uniformity illuminated with 100%. estimation from knife ? edge measurements ? 1.3?9.8 49.0 9.8?1.3 1.3?0.2 1.3?0.2 0.2?0.0 0.2?0.0 0.2?1.3 0.2?1.3 0.0?0.2 0.0?0.2 1.3 9.8 9.8 1.3
NOIH2SM1000A www.onsemi.com 35 package information pin type information the following conventions are used in the pin list. table 30. pin types ai analog input ao analog output ab analog bias di digital input do digital output vdd supply voltage gnd supply ground power supply considerations it is recommended to use one regulator for all digital supply pins together, one regulator for the sensor core analog supplies together, and one regulator for the adc analog supply (if used). analog ground returns must be of very low impedance, as short-term peaks of 200 ma can be encountered. the adc can be disabled by connecting all of its power and ground pins to system ground, leaving all other pins open. pin list doubled-up pins have the same pin name, but are indicated with (*). these pins are at the same potential on the chip. table 31. pin list pin no. name type purpose power supply and ground connections 10 vdd_dig (1) vdd logic power, 3.3 v 33 vdd_dig (2) vdd 11 gnd_dig (1) gnd logic ground 32 gnd_dig (2) gnd 8 vdd_ana (1) vdd analog power, 3.3 v 35 vdd_ana (2) vdd 9 gnd_ana (1) gnd analog ground 34 gnd_ana (2) gnd 55 gnd_ana (3) gnd 73 gnd_ana (4) gnd 58 vdd_pix (1) vdd pixel array power, 3.3 v 70 vdd_pix (2) vdd 74 vdd_res vdd reset power, 3.3 v, optionally up to 5 v for increased full well sensor biasing 75 gnd_ab ab anti-blooming ground, connect to system ground or to a low-impedance 1 v source for enhanced anti-blooming 52 nbias_dec ab connect with 200k to vdd_ana, decouple with 100 nf to gnd_ana 51 nbias_pga ab connect with 200k to vdd_ana, decouple with 100 nf to gnd_ana 50 nbias_uni40 ab connect with 75k to vdd_ana, decouple with 100 nf to gnd_ana 49 nbias_load ab connect to gnd_ana 48 nbias_precharge ab connect with 110k to vdd_ana, decouple with 100 nf to gnd_ana 47 nbias_prebuf ab connect with 200k to vdd_ana, decouple with 100 nf to gnd_ana 46 nbias_column ab connect with 110k to vdd_ana, decouple with 100 nf to gnd_ana analog signal input and outputs 31 signal_out ao output of pga, range ##.. ## v, straight polarity i.e. a low output voltage corres- ponds to a dark pixel reading. 60 a_in1 ai input to pga input multiplexer. 59 a_in2 ai input to pga input multiplexer.
NOIH2SM1000A www.onsemi.com 36 table 31. pin list pin no. purpose type name 57 a_in3 ai input to pga input multiplexer. 56 a_in4 ai input to pga input multiplexer. 54 photodiode ao reference photodiode logic control inputs and status outputs 71 a9 di parallel sensor programming interface shared address/data bus, msb 69 a8 di 68 a7 di 67 a6 di 66 a5 di 65 a4 di 64 a3 di 63 a2 di 62 a1 di 61 a0 di parallel sensor programming interface shared address/data bus, lsb 72 ld_y di load strobe: copy a[9..0] into y1 start register 76 ld_x di load strobe: copy a[9..0] into x1 start register 77 ld_reg di load strobe: copy a[7..0] into parameter register indicated by a[9..8] 78 res_regn di asynchronous reset for internal registers 82 sync_yrd di initialize y read shift register (yrd) to position indicated by y1 start register 84 sync_yrst di initialize y reset shift register (yrst) to position indicated by y1 start register 36 sync_xrd di initialize x read shift register (xrd) to position indicated by x1 start register 83 clk_yrd di advance shift register yrd one position 1 clk_yrst di advance shift register yrst one position 25 clk_x di advance shift register xrd; note: two clock cycles needed for one pixel output 53 eos do end of scan monitor output for yrd,yrst,xrd shift registers, selected through an internal register 2 yrst_yrdn di enable yrd to address the pixel array when ?0?; enable yrst to address the pixel array when ?1? 4 reset di reset the line pointed to by yrst (yrst_yrdn = ?1?) or pointed to by yrd (yrst_yrdn = ?0?) 37 blank di assert when in line blanking / non-readout phase 3 sel di select for readout the line pointed to by yrst (yrst_yrdn = ?1?) or yrd (yrst_yrdn = ?0?) 5 precharge di pre-charge column bus 6 r di sample the selected line?s levels onto the column amplifier reset level bus 7 s di sample the selected line?s levels onto the column amplifier signal level bus 38 cal di calibrate pga adc 30 in_adc ai analog input to adc 27 clk_adc di adc conversion clock, pixel rate, latency is 6.5 cycles 23 data_11 do adc data output, msb 22 data_10 do
NOIH2SM1000A www.onsemi.com 37 table 31. pin list pin no. purpose type name 21 data_9 do 20 data_8 do 19 data_7 do 18 data_6 do 17 data_5 do 16 data_4 do 15 data_3 do 14 data_2 do 13 data_1 do 12 data_0 do adc data output, lsb 43 spi_din di serial calibration interface data in 42 spi_ld di serial calibration interface load strobe 41 spi_clk di serial calibration interface bit clock 44 adc_nbias ab connect with 60 k resistor to adc_pbias, decouple with 100 nf to ground 45 adc_pbias ab connect with 60 k resistor to adc_nbias, decouple with 100 nf to vdd_adc_ana 39 vlow_adc ai adc low threshold reference voltage, connect with 90 to gnd and 130 to vhigh_adc, decouple with 100 nf to ground 40 vhigh_adc ai adc high threshold reference voltage, connect with 130 to vdd_ana_adc, decouple with 100 nf to ground 81 ref_comp_low ao decouple with 100 nf to ground 80 ref_mid ao decouple with 100 nf to ground 79 ref_comp_high ao decouple with 100 nf to ground 29 vdd_adc_ana vdd analog supply, 3.3 v 28 gnd_adc_ana gnd analog ground 24 vdd_adc_dig vdd digital supply, 3.3 v 26 gnd_adc_dig gnd digital ground
NOIH2SM1000A www.onsemi.com 38 electrical characteristics multiplexer inputs table 32. multiplexer inputs pin no. name input impedance settling time 60 a_in1 capacitive 10 pf 100 ns 59 a_in2 capacitive 10 pf 100 ns 57 a_in3 capacitive 10 pf 100 ns 56 a_in4 capacitive 10 pf 100 ns digital i/o d c si mulation of differ ent input buffers of has 2 0.00e+00 5.00e-01 1.00e+00 1.50e+00 2.00e+00 2.50e+00 3.00e+00 3.50e+00 0.00e+00?5.00e-011.00e+00?1.50e+00?2.00e+00?2.50e+00?3.00e+00?3.50e+00 digit al input output of buffert incertain if input is seen as a high or low signal high signal, but leackage current through buffer high signal low signal, but leackage current through buffer low signal figure 24. simulation results digital ?0? and digital ?1?
NOIH2SM1000A www.onsemi.com 39 package pin assignment the has sensor is packaged in an 84-pin jlcc84 package with large cavity. the following figure shows the pin configuration. figure 25. pin configuration
NOIH2SM1000A www.onsemi.com 40 user manual image sensor architecture figure 26. sensor block diagram pixel architecture a square array contains 1024 x 1024 three-transistor linearly-integrating pixels of each 18 x 18 m. each pixel has a connection for a reset line, for power, an output select line, and eventually the pixel?s output signal. figure 27. three ? transistor pixel: transistor ? level diagram (left), and functional equivalent (right) ? v reset? dd? out? select? v reset dd out?? select
NOIH2SM1000A www.onsemi.com 41 there are three transistors in a pixel. the first one acts as a switch between the power supply and the photodiode. the photodiode is equivalent to a capacitor with a light-controlled current source. the second transistor is a source follower amplifier, buffering the voltage at the photodiode/capacitor cathode for connection to the outside world. the third transistor again is a switch, connecting the output of the buffer amplifier to an output signal bus. activating the reset line drains the charges present on the pixel?s embedded photodiode capacitor, corresponding to a black, dark, pre-exposure state, or high voltage. as all pixels on a row (line) share their reset control lines, the pixels in a row can only be reset together. with both reset and select lines disabled the pixel amasses photo charges on its capacitor, charges generated in the photodiode by impinging photons. during this integration the voltage on the photodiode cathode decreases. when the select line is asserted the voltage on the capacitor is connected to the pixel output through the source follower buffer transistor. all pixels in a line have their select lines tied together: upon selection a whole line of pixel output signals is driven onto the 1024 column buses that lead into the column amplifiers for further processing and complete or partial sequential readout to the adc. all pixels on a line have their reset lines tied together: the reset mechanism works on all pixels in a line simultaneously, no individual or addressed pixel reset (ipr) is possible. figure 28. signal lifetime in a three ? transistor pixel: reset to black level (high voltage), photo charge integration (dropping voltage), voltage readout output level empty well full well exposure time post-integration output level pixel time reset exposure readout figure 29. front view of sensor die: package pin 1 is on the left side. the focal plane origin is in the bottom ? left corner. lines (y) are scanned down to top, pixels (x) left to right y x (0,0)
NOIH2SM1000A www.onsemi.com 42 line addressing the sensor operates line wise: a line of pixels can be selected and reset, and a line of pixels can be selected for readout into the column amplifier structures. there is no frame reset operation, there is no frame transfer. image acquisition is done by sequencing over all lines of interest and applying the required reset and/or readout control to each line selected. the sensor array contains two vertical shift registers for line addressing. these registers are one-hot; they contain a pattern such as ?00001000000?, at each time pointing to one line of pixels. figure 30. line addressing structures: yrd and yrst one ? hot shift register pointers and y1 programmable start ? of ? scan register 0 0? 0? 0? 0? 0? 0? 0? 0 0 ? 0? 0? 0? 0? 1? 0? 0? 0 ? yrd ? yrst y1? line selected by yrd when yrst_yr dn=?0? register upload yrst_yrd b clk_yrd? clk_yrst? sync_yrd ? sync_yrst ? line selected by yrst when yrst_yr dn=?1? in double sampling and destructive readout, one of these registers is typically dedicated to addressing the lines to read, and the other is used for addressing the lines to reset as part of the electronic shutter operation. in correlated double sampling and nondestructive readout, you can choose if one or both shift registers will be used. both y shift registers can be initialized to a position indicated by an on-chip address register. this address register is written by the user through the parallel sensor programming interface. with this programmable initial position windowed readout (region-of-interest) is possible. both registers can be advanced one position at a time under user control. pixel addressing pixels are read from left to right, generating a pixel-sequential output signal for each line. the pixel addressing is similar to the line addressing. close to the column amplifiers resides a horizontal shift register for pixel/column addressing. this register is one-hot; it contains a pattern such as ?00001000000?, at a time pointing to exactly one pixel and one column amplifier. line acquisition is done by sequencing over all pixels of interest and applying each time the required pixel readout and adc control signals. the x shift register can be initialized to a position indicated by an on-chip address register. this address register is written by the user through the parallel sensor programming interface. with this programmable initial position windowed readout (region-of-interest) is possible. the x register can be advanced one position under user control. this requires a pixel clock signal at twice the frequency of the desired pixel rate. column amplifiers at the bottom of each column of pixels sits one column amplifier, for sampling the addressed pixel?s signal and reset levels. these signals are then locally hold until that particular pixel is sent to the output channel, in this case pga, multiplexer, buffer, and adc.
NOIH2SM1000A www.onsemi.com 43 the combination of column amplifiers and pga can perform double sampling: in this case a pixel?s signal level is read into the structures, then the pixel is reset, then the reset level is read into the structures and subtracted from the previously-stored signal level, cancelling fixed pattern noise. in correlated double sampling mode the column amplifiers are used in bypass mode, and the raw signal level (which can be either a dark reset level or a post-illumination signal level) is sent to the output amplifier, and then to the output for storage and correlated subtraction off-chip. this cancels fixed pattern noise as well as temporal ktc noise. input signal multiplexer an analog signal multiplexer with six inputs connects a number of sources to the output buffer. one input always is connected to the pixel-serial output of the pixel array. four inputs are connected to analog input pins and are intended for monitoring voltages in the neighborhood of the sensor. the last multiplexer input is connected to the on-chip temperature sensor. the multiplexer is controlled by an internal register, written through the parallel sensor programming interface. programmable gain amplifier (pga) a voltage amplifier conditions the output signal of the multiplexer for conversion by the adc. signal gain and offset can be controlled by a register written through the parallel sensor programming interface. when connected to the pixel array, the pga also subtracts pixel black level from pixel signal level when in ds/dr mode. parallel sensor programming interface the sensor is controlled via a number of on-chip settings registers for x and y addressing, pga gain and offset, one-off calibration of the column amplifiers. these registers are written by the user through a parallel bus. 12 ? bit analog to digital convertor (adc) the on-chip adc is a 12 bit pipelined convertor. it has a latency of 6.5 pixel clock cycles, i.e. it samples the input on a rising clock edge, and outputs the converted signal 6 pixel clock periods afterwards on the falling edge. the adc contains its own spi serial interface for the optional upload of calibration settings, enhancing its performance. the adc is electrically isolated from the actual sensor core: when unused it can be left non-powered for lower dissipation, and without risk for latch-up. when used, the input voltage range of the adc is set with a two-node voltage divider connected to pins vlow_adc and vhigh_adc. the adc has an accuracy of 10 bit at 5 mhz operation speed. temperature sensor a pn-junction type temperature sensor is integrated on the chip. the temperature-proportional voltage at its output can be routed to the adc through one of the six analog inputs of the multiplexer. the temperature sensor must be calibrated on a device-to-device base. its nominal response is ?4.64 mv/ c. image sensor operation the following section describes the has2 readout mechanisms and gives the detailed timing and control diagrams to implement these mechanisms. double sampling ? destructive readout in double sampling or destructive readout (ds/dr) mode the yrst pointer runs over the frame, top to bottom, each time resetting the line it addresses. lagging behind this runs the yrd pointer, each time reading out the line it addresses. the distance between the yrd pointer and the yrd pointer is then proportional to the exposure time, hence the electronic shutter operation. at line readout the signal levels of the pixels in the addressed line are copied onto the column amplifiers? signal sample nodes. immediately after this the line of pixels is reset, and the pixels? black levels are copied onto the column amplifiers? reset sample nodes. this is destructive readout. the column amplifiers/pga then subtract the black levels from the signal levels during sequential pixel out. this is un-correlated double sampling, eliminating any static pixel-to-pixel offsets of the sensor array.
NOIH2SM1000A www.onsemi.com 44 figure 31. double sampling: pixel signal is read (s), then pixel is reset, then reset level is read (r) r: non ? correlated reset level time output level pixel empty well full well texp pixel output = (s ? r) s: pixel signal level correlated double sampling ? nondestructive readout in correlated double sampling or nondestructive readout (cds/ndr) mode the yrst or yrd pointer quickly runs over the frame, top to bottom, resetting each line it addresses. this leaves the pixel array drained of charges, in black or dark state. then the yrd or yrst pointer is run over the region of interest of the frame, and of each line addressed the pixels? black levels are read out and passed on to the adc. the user stores these black levels in an off-chip frame-sized memory. then the system is held idling during the exposure time. after the exposure time has elapsed, the frame is scanned once more with the yrd or yrst pointer, and each line addressed is read out again. these signal levels are passed on to the adc and then to the end user. at the same time, the user retrieves the corresponding black levels from the memory and subtracts them from the signal levels. this is correlated double sampling, eliminating static offsets as well as ktc noise figure 32. correlated double sampling: pixel is reset, reset level is read and stored (r), pixel is exposed, signal level is read (s), difference is output s: pixel signal level, output (s ? r) difference sram r: correlated reset level, store in pixel out put level empty well full well texp frame time time possible exposure times the range of exposure times attainable by the has is entirely dependent on the user control strategy, although two obvious scenarios can be envisaged: in destructive readout/double sampling, a typical case is a minimal exposure time equal to the line readout time, and a maximal exposure time equal to the frame time. with 1024 x 1024 pixels in a frame, 10 frames per second, this amounts to 98 s and 100 ms. in nondestructive readout/correlated double sampling it is not even possible to pinpoint a typical case, as all depends on the exact reset (r), reset-read (r) and signal-read (s) scheme the user employs. in the specific case of 10 mhz pixel rate rate operation, 10 windowed frames per second, and 40 windows of 20 x 20, each receiving the same exposure time, and the whole fpa reset (r) at the start of the frame, the minimal exposure time is 7.3 ms, the maximal exposure time 90.2 ms. depending on window configuration, shorter and longer times are possible, though.
NOIH2SM1000A www.onsemi.com 45 timing and control sequences definitions the has is a line-scan imager with 1024 horizontal lines (y) each of 1024 pixels (x). pixel coordinates are defined relative to an origin (x=0,y=0), and projected onto the user?s display view: the origin (0,0) is in the top-left corner of the displayed image, lines are scanned top-down, and the pixels in a line are scanned left to right. windows or regions-of-interest are defined by their top-left and bottom-right coordinates (x1,y1)-(x2,y2). the full frame then corresponds to (0,0)-(1023,1023). note that (x1,y1) is to be programmed into the sensor, while (x2,y2) is not: windowed readout is obtained by pointing the sensor to (x1,y1), followed by reading out (y2-y1+1) lines of (x2-x1+1) pixels. a frame readout sequence consists of a number of line readout sequences. a line readout sequence consists of ? a line select sequence for the yrd and yrst pointer shift registers, during which a line may be selected for readout and another line may be selected for reset ? a line blanking sequence during which the line selected for readout copies its pixel signals into the column amplifiers, the column amplifiers are operated, and both lines selected are optionally reset (the line selected for read can be reset as part of the destructive readout/double sampling operation; the other line can be reset as part of the electronic shutter operation). ? a pixel readout sequence a pixel readout sequence consists of ? initialization of the pixel pointer xrd to position x1 ? a sequencing through the region-of-interest, ? while the output amplifier and the adc are activated and pixel values are sequentially selected, connected to the pga, and converted by the adc. figure 33. line selection timing diagram blank? clk_y*? sync_y*? y*? y1? y1+1 y1+2 y1+3 y1+4? xxx? t 1 ? t 2 ? t 3 t 4 t 5 this timing diagram is valid for clk_yrd/sync_yrd and for clk_yrst/sync_yrst. description min typ max remarks t 1 sync_y* setup 50 ns t 2 clk_y* high width 100 ns t 3 clk_y* period 200 ns no constraint on duty cycle t 4 address delay 30 ns t 5 setup to next blanking 100 ns
NOIH2SM1000A www.onsemi.com 46 destructive readout timing diagram in this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. hence, the exposure time texp can be expressed as an equivalent number of lines. table 33. threads of operation for destructive readout with double sampling comment yrd - read side yrst - reset side init load registers y1 and x1 with the window start coordinates initialize yrd with y1 initialize yrst with y1 expose .do nothing for yrst = y1 to y1+texp loop .select line yrst .reset line yrst .wait for one line time .advance yrst one position end loop read for yrd = y1 to y2 loop .select line yrd .operate column amplifiers for ds/dr .read pixels x1 to x2 .advance yrd end loop .select line yrst .reset line yrst .advance yrst figure 34. ds/dr sequence: exposure is initiated with running yrst over the array, resetting lines. after texp yrd starts running over the array too, reading and then resetting lines figure 35. destructive readout timing diagram blank? precharge? sel? reset? yrst_yrdn ? s? r? 1 t ? 4 t ? 2 t ? 3 t ? 8 t 6 t ? 7 t 5 t ? 9 t 10 t 2 t 3 t 4 t 11 t 15 t 13 t 7 t ? 12 t 14 t ? 13 t ? double sampling of line indicated by yrd optional reset of yrst for electronic shutter pixel readout cal? 16 t ? 16 t ?
NOIH2SM1000A www.onsemi.com 47 description min typ max remarks t 1 blank setup 13 ns 25 ns t 2 s setup 10 ns 25 ns t 3 precharge width 400 ns t 4 30 ns 50 ns t 5 s active when sel 2 s t 6 11 ns 25 ns t 7 reset width 400 ns t 8 100 ns t 9 100 ns t 10 r active when sel 2 s t 11 10 ns 25 ns t 12 yrst_yrdn setup 100 ns second reset is optional t 13 yrst_yrdn hold 100 ns t 14 blank hold 22 ns 25 ns t 15 blank hold 100 ns when no second reset t 16 cal delay ref. blank 25 ns once per frame or per line the cal signal initiates the programmable gain amplifier to a known ?black? state. this initialization should be done at the start of each frame. nondestructive readout timing diagram in describing this mode, the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. hence, the exposure time texp can be expressed as an equivalent number of lines. (note that the user is under no obligation to link texp to the line read time: texp can be chosen arbitrarily as its timing and nature are only dependent on the external system controlling the has). table 34. threads of operation for nondestructive readout with off ? chip cds comment yrd - read side yrst - reset side init load registers y1 and x1 with the window start coordinates initialize yrd with y1 initialize yrst with y1 clear frame .do nothing for yrst = 1 to 1023 loop .select line yrst .reset line yrst .advance yrst one position end loop read black levels for yrd = y1 to y2 loop .select line yrd .operate column amplifiers for cds/ndr, black levels .read pixels x1 to x2 .advance yrd end loop exposure wait for time texp read signal levels for yrd = y1 to y2 loop .select line yrd .operate column amplifiers for cds/ndr, signal levels .read pixels x1 to x2 .advance yrd end loop proper operation can be attained by using just one y pointer register, yrd or yrst, for all of the frame?s phases. the above operation scheme is just an example, using yrst for the frame reset phase.
NOIH2SM1000A www.onsemi.com 48 figure 36. cds/ndr sequence: first array is reset completely with yrst. then black levels are read with yrd. then, after a time texp, all signal levels are read, again with yrd. figure 37. non ? destructive readout timing diagram k blan ? pre charge? l se ? t rese ? yrst_yrdn? s? r? 1 t ? ? res e t of line yr d readout of line yrd black or signal levels ? pix el readout 2 t ? 3 t ? 2 t ? 1 t ? 5 t 4 t 6 t 7 t 8 t 9 t 10 t ? 11 t ? l ca ? ? 12 t ? 12 t description min typ max remarks t 1 blank setup 13 ns 25 ns t 2 yrst_yrdn s/h 100 ns optional, only when yrst is used instead of yrd t 3 reset width 400 ns t 4 blank setup 13 ns 25 ns t 5 s/r setup 10 ns 25 ns t 6 precharge width 400 ns t 7 30 ns 50 ns t 8 s/r active when sel 2.4 s t 9 11 ns 25 ns t 10 sel hold 11 ns 25 ns t 11 blank hold 100 ns t 12 cal delay ref. blank 25 ns once per frame or per line/window
NOIH2SM1000A www.onsemi.com 49 figure 38. pixel readout timing diagram cal? clk_x? sync_x? xrd? output ? signal? x1? x1+1? x1+2? x1+3? x1+4? xxx? clk_adc? x1 x1+1? x1+2 2 t 3 t 1 t 4 t ? the externally applied clock clk_x runs at twice the pixel rate. from address pointer xrd shift to output signal available exists a latency of 6 clk_x cycles. the above timing diagram supposes an adc sampling at the rising edge of clk_adc. description min typ max remarks t 1 clk_x period 50 ns 100 ns 50% duty cycle required, 2.5 ns t 2 output settle time 15 ns t 3 output hold time 2 ns t 4 cal off setup 50 ns blank off setup when no cal pga and signal multiplexer control figure 39. programmable gain amplifier and signal multiplexer diagram pga? mux buffer temp a_in1 a_in2 a_in3 a_in4 t signal_ou ? amp.offset[5..0]? amp.gain[1..0] ? pixels? mode.pga[2..0] cal? figure 40. amplifier calibration timing diagram clk_x? cal? t 1 t 2
NOIH2SM1000A www.onsemi.com 50 the column amplifier output is a stream of raw or fpn-corrected pixels. these pixels then pass the programmable gain amplifier, where gain and dc-offset can be adjusted. then follows a signal multiplexer that selects between the pixel signal or the temperature sensor and four externally-accessible analog inputs. the output of the multiplexer is buffered and then made available at output pad signal_out. the pga must be calibrated periodically with a black reference input signal, triggered by cal. after each change of the gain settings, the pga have to be calibrated to set the correct offs et on the pga. it is suggested to make this cal signal equal to the blank signal. note: the blank signal resets the x shift register. so after each active blank period, there has to be a syncing of the x shift register before reading out any pixel. for gain and offset control, see section ?sensor programming? on page 51. description min typ max remarks t 1 cal width 200 ns t 2 cal-to-pixel-readout 50 ns multiplexer operation mode.pga[2..0] selected input 000 pixel array 001 temp 010 - 011 - 100 ain1 101 ain2 110 ain3 111 ain4 changing gain during read out it is possible to change the gain settings during the read out of one line. the following procedure is suggested. for example, gain changing between pixel 56 and 57. ? when pixel 56 comes out, stop the x clock after the falling edge. ? the output stays at the same level of this pixel (see figure 38 on page 49) ? change the gain settings by setting the internal registers as described in sensor programming on page 51 ? assert the cal signal for 200 ns but leave the blank signal inactive ? after the cal signal has felled down, wait 50 ns. ? reactivate the x clock starting with the rising edge ? the first pixel that comes out is pixel 57 the total time needed to change the gain settings is about 450 ns. hard reset ? soft reset ? hard ? to ? soft reset see reset modes timing controls on page 56. figure 41. adc timing diagram analogue? in? c clk_ad ? data[11..0] ? 1 xxx? 2 3? t 1 t 2 t 3 t 4 t 5 the adc is a pipelined device that samples on each rising edge of its clock clk_adc. the output data is updated on each falling edge of clk_adc. there is an input-to-output latency of 6.5 clock cycles. description min typ max remarks t 1 input setup 5 ns t 2 input hold 20 ns t 3 sample clock 100 ns 50% duty cycle required, 5% t 4 latency 6.5 t 3 exact t 5 output delay 10 ns
NOIH2SM1000A www.onsemi.com 51 sensor programming parallel sensor programming interface the operational modes and start-of-window addresses of the has are kept in seven on-chip registers. these internal registers are programmable through a parallel interface similar to the one on the star250. this interface comprises of a 10-bit wide a bus, and 3 load strobes: ld_x, ld_y, and ld_reg. with ld_y or ld_x asserted (rising edge), the full 10 bits of a are loaded into respectively the line start address (y1) and the column start address (x1) (as similar to the star250). with a rising edge on ld_reg, the upper two bits of a are decoded as an internal register address, and the 8 lower bits of a are loaded into the corresponding register. these 4 registers are reset to their default values by asserting res_regn. address register load timing diagram figure 42. line / column address upload timing diagram a? ld_x/ld_y? xxx? x1/y1? t 1 x1/y1? x1/y1 t 4 t 2 t 3 the yrd/yrst and xrd pointer start address registers y1 and x1 are latches that pass the input value when ld_y/ld_x is asserted, and freeze their output values when ld_y/ld_x is deasserted. description min typ max remarks t 1 a setup 100 ns t 2 ld_* width 100 ns t 3 delay 75 ns t 4 a hold 100 ns figure 43. mode registers upload timing diagram a? ld_reg? register ? xxx? t 1 value value t 2 t 3 t 4 the mode setting registers are edge-triggered flip flops that freeze their outputs at the rising edge of ld_reg. description min typ max remarks t 1 a setup 100 ns t 2 ld_reg width 100 ns t 3 delay 75 ns t 4 a hold 100 ns
NOIH2SM1000A www.onsemi.com 52 internal registers global description are registers are programmed using the parallel upload interface. two styles of register access methods are used. address registers loaded with ld_y or ld_x: register name value a[9..0] default description y1 9:0 0 start position of the yrd and yrst one-hot addressing shift registers, range 0..1023 x1 9:0 0 start position of the xrd one-hot pixel address register, range 0..1023 mode registers loaded with ld_reg and reset to default with res_regn: register name address a[9..8] value a[7..0] default description mode 00 6:5 0 end of scan multiplexer 4:2 0 pga input multiplexer 1 0 1 = nondestructive readout 0 = destructive readout, dual sampling 0 0 1 = standby 0 = aps in active mode amp 01 7:2 0 amplifier raw offset 1:0 0 amplifier gain. black 10 7:0 0 ndr mode black level offset 11 7:0 0 dr mode column bus offset correction internal registers detailed description x1 register: x1 strobe: ld_x a[9..0] = x1[9..0] x1[9..0] start coordinate of xrd shift register for pixel scan y1 register: y1 strobe :ld_y a[9..0] = y1[9..0] y1[9..0] start coordinate of yrd and yrst shift registers for line scan legal (decimal) values are 0 (first line of the array) to 1023 (last line of the array)
NOIH2SM1000A www.onsemi.com 53 mode register: mode a[9..8] = ?00? ld_reg a[7..0] = ?x?&eos[2..0]&pga[2..0]&ndr&standby eos[1..0] end-of-scan indicator selector 00 output of yrd shift pointer register to pin eos 01 output of yrst shift pointer register to pin eos 10 output of xrd shift pointer register to pin eos 11 output of xrd shift pointer register to pin eos pga[2..0] pga input multiplexer 000 pixel array 001 temp temperature sensor 010 - 011 - 100 ain1 analog telesense input 101 ain2 110 ain3 111 ain4 ndr non-destructive readout selector 0 ndr off, ds/dr enabled 1 ndr on, cds/ndr enabled standby power switch 0 sensor operational 1 sensor in standby / low power eos[1..0] connects the output of the last stage of either one of the internal array = addressing shift register pointers yrd, yrst or xrd to the outside world at pin eos. pga[2..0] selects one of 6 possible analog signals to be connected to the analog output pin. ndr selects dr or ndr mode. standby puts the sensor in a low-power mode, in which the current mirror bias network drivers of the column structures, pga, output buffer, and internal offset dacs are disabled. amp a[9..8] = ?01? ld_reg a[7..0] = offset[5..0]&gain[1..0] offset[5..0] pga offset gain[1..0] pga gain 00 1 01 2 10 4 11 8
NOIH2SM1000A www.onsemi.com 54 this register sets the pga output offset and gain. the pga output signal offset is controlled in 64 steps of 16 mv each, from 0.3 v to 1.3 v. output offset control is used to adapt the pgas output to the adc used (internal or external adc). see other definitions on page 13. for unity gain and internal adc use, the recommended default setting is: amp_offset = 60 the reset value of amp.offset is 0, decoding to the middle offset value of 0.8 v. amp.of fset range 0 to 31 corresponds to levels of 0.8 to 1.3 v, while amp.offset range 32 to 63 corresponds to levels of 0.3 to 0.8 v. gain is controlled in 4 steps for nominal values of 1,2,4, and 8. real gain values are expected to be somewhat lower and will be characterized. black register: black a[9..8] = ?10? ld_reg a[7..0] = black[7..0] black[7..0] ndr mode black level the black register sets the black level of the column amplifier structures and column pre-chargers when used in ndr mode. the reset value of black is 0, setting the internal black level to half-way full scale: black range 0..127 corresponds to 1.65 v to 2.9 v in steps of 10 mv. black range 128 to 255 corre sponds to 0.4 v to 1.65 v in steps of 10 mv. the recommended default setting is: black = 10 offset register: offset a[9..8] = ?11? ld_reg a[7..0] = offset[7..0] offset[7..0] column bus offset correction. the column signal path and later parts of the signal path is split in an odd bus with amplifiers and an even bus with amplifiers. using the offset register, the offsets for these two signal paths can be calibrated to obtain a balanced performance. the reset value of offset is 0, driving the offset generator to half-scale (0 mv). offset range 0 to 127 corresponds to 0 to +17.5 mv in steps of 140 v. offset range 128 to 255 corresponds to ?17.5 mv to 0 mv in steps of 137 v. expressed in electrons, this gives the following numbers: total offset correction range: 2365 electrons step of correction: 9.3 electrons the recommended default setting is: offset = 0 (sample depended). it?s recommended to calibrate the device while taking a dark image. sensor calibration ndr mode black level black=10. column amplifier offset correction the column amplifier structures comprise of two independent signal buses, one handling pixels from odd columns, one handling pixels from even columns. as these structures are inherently imperfectly matched in offset, user calibration of this parameter is required when the sensor is operated in destructive readout / double sampling mode. the default (reset) values for this parameter puts the internal calibration signal generators in their neutral, middle-value mode. adc corrections concept the adc is a pipelined device with 11 identical conversion stages in series. each conversion stage is built around an amplifier with gain that can be calibrated. each amplifier?s gain can be tuned individually with an 8 bit code, totaling 11 words of 8 bits to be loaded into the adc through a separate serial interface. adc tuning codes tuning codes each span the range 0 to 255, with value 127 denoting the amplifier?s central gain setting (default after power-on, i.e. without user calibration, and allowing nominal operation of the device). code 0 reduces the gain
NOIH2SM1000A www.onsemi.com 55 with 5%, tuning code 255 increases gain with 5%. the code-gain relation is guaranteed monotonous. adc linearity tuning method the ideal calibration code is 75 for each stage. it is expected that a complete set of calibration values will be provided in the sensor data sheet, or when necessary, with each device individually. figure 44. adc serial interface spi_clk? spi_data? xxx? ? t 1 n ? n\ 1 1? spi_ld? xxx t 2 t 3 description min typ max remarks t 1 spi_clk width 1000 ns t 2 spi_ld setup 0 ns t 3 spi_ld width 1000 ns all 11 8-bit correction words are uploaded in one burst of 88 bits. the word for stage 11 first, then stage 10, and so down to stage 1. w ithin each word the msb comes first. bits are sampled on the rising edge of spi_clk, and thus should change on the falling edge of spi_clk. the complete set of words is registered in the adc on the rising edge of spi_ld. sensor biasing the operating points of the sensor and adcs analog circuitry are set with external passive components (resistors and capacitors). these components have their recommended values listed in detailed information on page 3. adc input range setting the input voltage range of the adc (pin adc_in) is to be matched to the signal at hand, in this case the output voltage range at pin signal_out. the lower threshold is set to the voltage injected at pin vlow_adc. the upper threshold is set to the voltage injected at pin vhigh_adc. for both settings it is recommended to use a resistive voltage divider: 90 from gnd_adc_ana to vlow_adc, 130 from vlow_adc to vhigh_adc, 130 from vhigh_adc to vdd_adc_ana. temperature sensor an internal temperature sensor presents a temperature-dependent voltage which can be made available at pin signal_out through the multiplexer. the voltage-temperature dependency is approximately ?4.64 mv/ c, but the absolute level is to be characterized on a device-by-device basis for demanding applications. with the on-chip adc biased for an input window of 0.7 to 1.9 v, the temperature sensor/adc combination can be used from ?40 to +125 c.
NOIH2SM1000A www.onsemi.com 56 reset modes timing controls figure 45. hard reset 0 v 4.2 v 400 ns 3.3 v 0 v vdd_pix reset figure 46. soft reset 0 v 3.3 v 400 ns 3.3 v 0 v reset vdd_pix figure 47. hard to soft reset 0 v 3.3 v 400 ns 3.3 v 0.75 v reset vdd_pix 400 ns
NOIH2SM1000A www.onsemi.com 57 application and test circuits figure 48. sensor pinning all ground pins may be connected to 1 point except the anti blooming ground (gndab). the reference voltages can be either injected by a power supply voltage or can be generated from a resistance divider. see adc input range setting on page 55.
NOIH2SM1000A www.onsemi.com 58 figure 49. sensor biasing circuits figure 50. sensor power supply decoupling circuits figure 51. reference voltage end circuits figure 52. sensor adc circuitry
NOIH2SM1000A www.onsemi.com 59 acronyms for the purpose of this specification, the terms, definitions, abbreviations, symbols, and units specified in escc basic specification 21300 apply. in addition, the following table contains terms that are specific to cmos image sensors and are not listed in escc21300 abbreviation description adc analog to digital convertor aps active pixel sensor cds correlated double sampling dnl differential nonlinearity dr destructive readout dsnu dark signal non-uniformity eppl european preferred parts list esd electro-static discharge fpn fixed pattern noise has high accuracy star tracker inl integral nonlinearity mtf modulated transfer function ndr nondestructive readout prnu pixel response non-uniformity tbc to be confirmed tbd to be defined rga residual gas analysis
NOIH2SM1000A www.onsemi.com 60 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. conversion gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. cfa color filter array. the materials deposited on top of pixels that selectively transmit color. dnl differential nonlinearity (for adcs) dsnu dark signal non-uniformity. this parameter characterizes the degree of non-uniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixel array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response non-uniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is oper- ated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodi- ode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wave- length. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
NOIH2SM1000A www.onsemi.com 61 frequently asked questions question: in the has2 data sheet, the pixel readout timing diagram lacks information. it appears sync_x should change on the rising edge of clk_x. while sync_x is high, a rising edge of clk_x should sync xrd to x1 register. but the diagram shows sync_x high for two clk_x periods. due to timing variations, sync_x can be high for as many as three dif ferent rising edges of clk_x! the timing diagram does not show any setup or hold timing for sync_x and clk_x. answer: clk_x is divided internally in the sensor. sync_x is based upon this divided clock. when sync_x is high for an even pair of this divided clock cycles, the xrd is pushed the length of this even pair of clock cycles. though, when sync_x drops during an uneven pair of divided clock cycles, it is unclear what xrd will do. but this behavior is most unlikely. question: res_regn does not have any timing information. it is the asynchronous reset for internal registers. how long must it be held low? answer: to be on the safe side, keep it low for at least 1 s. you can apply the following sequence when powering up the sensor: ? power on device with known register settings ? during power on, keep res_regn low for at least 1 s ? apply line/column address upload timing diagram question: the adc serial interface timing diagram is incomplete. it appears the spi_data is supposed to change on the falling edge of spi_clk. if so, then what is the setup and hold times of the spi_data around the rising edge of spi_clk? the spi_clk has a period of 1000 ns, so the spi_data is present for 500 ns prior to the rising edge of spi_clk. but what is the spi_data setup time for the *first* rising edge of spi_clk (first bit of data)? answer: the best way to operate the device is to change your spi data during the falling edge of the spi clock. this gives you plenty of time before the data is being sampled on the rising edge of the spi clock. consider a 100 ns hold and setup time of the spi data around the rising edge of the spi clock. for the first rising edge, consider a 500 ns setup time for the spi data. question: i noticed that blank remains high for the destructive readout timing diagram even during the reset of yrst row. however, in the nondestructive readout timing diagram, blank is shown going low between a reset and line selection, with no timing information. what should the timing be? or should it be left blank constantly high during a line reset and subsequent line selection during nondestructive readout? answer: for the nondestructive read out, extend t1 and reduce t4. this means that you can leave the blank signal high.
NOIH2SM1000A www.onsemi.com 62 blank? precharge? sel? reset? yrst_yrdn? s? r? 1 t ? reset of line yrd readout of line yrd black or signal levels pixel readout 2 t ? 3 t ? 2 t ? 1 t ? 5 t 4 t 6 t 7 t 8 t 9 t 10 t ? 11 t ? cal? 12 t ? 12 t question: what is your recommendation to do with the unused analog inputs to the multiplexor (a_in1-4)? grounding them will place them at 0 volts, which is outside the vlow_adc range. should they be left floating? or should they be tied to some constant voltage source between vhigh_adc and vlow_adc? answer: if you do not use the analog inputs, then ground them. but most customers use these inputs to monitor some supply voltages. for example, monitor your 3.3 v input voltage. divide it with a resistance divider to have the voltage inside the adc range. you can also use it to monitor some external voltages that are used on your board and which are important to be stable. question: what are the implications of turning off the analog power supplies (vdda), but keeping the digital power supply (vdd) active? i am trying to improve the standby low power mode. answer: no this is not bad. in fact, the total power supply current will reduce a little more. question: specification sheet describes the adc input range setting: 90 from gnd_adc_ana to vlow_adc, 130 from vlow_adc to vhigh_adc, 130 from vhigh_adc to vdd_adc_ana. the vdd_adc_ana is 3.3 v so this puts vlow_adc = 0.85 v and vhigh_adc = 2.07 v. table 28 on page 23 specifies adc_vlow = 0.8 v and adc_vhigh = 2.5 v. which way do you recommend? can you describe the discrepancy? answer: the correct adc range is with the resistance divider. an alternative without resistance divider is to directly inject this voltage by a power supply circuitry. this is how it is done in our characterization system. this way, you can tune adc settings as required. however, to retain the resistances, use the values described above. table 28 on page 23 is a typo. it should be 0.85 v and 2.0 v. question: in the data sheet, adc high/low bias voltages are recommended to be set with a resistive divider. but the data sheet does not mention anything about temperature stability. for the star-1000, there is an internal resistor between adc_high and adc_low that had temperature dependence. because of this, for star-1000 designs, i set my adc bias voltages with buffers that keep the bias levels constant over temperature. do i need to repeat the same principle for the has2? or does the has2 remove any temperature dependence for the adc bias voltages? answer: for good temperature stability, it is better to use the same principle as the st ar-1000. so use external buffers to keep adc_high and adc_low to a fixed voltage level. question: for figure 41 on page 50 , the table lists t5, output delay, as typically 10 ns. the star-1000 had a troublesome output delay variability of 20 ns to 60 ns, some parts even had 70 ns! have the digital output drivers been significantly improved for the has2 adc? what are typical rise/fall times for the outputs? answer: the output delay and stability has been improved compared to star-1000. question: what are the differences between blank, cal, and precharge? the star-1000 only had a cal signal. answer: the extra blank signal is used to reset the internal clkx divider. precharge is used to pre-charge the column lines and column caps to ground
NOIH2SM1000A www.onsemi.com 63 question: the has2 appears more restrictive compared to the flexibility of star-1000. for example, the application note says, ?repeated use of pixel re-addressing (register x1) potentially injects offset-noise into any windows that overlap in y-coordinates.? does this mean i cannot address each pixel along a line individually? i cannot read out every other pixel, or every second, fifth, or tenth and all pixels must be read out in a line. are there any options? answer: you can start reading at any x or y position. remember that there is an analog pipeline on the pixel data. when reading two pixels of the same line closer than the analog pipe, the second pixel is addressed only after the first pixel. therefore, the second pixel is read by a new syncx, when yo address it the second time. as a result, there is a risk of a deviated value. probably some deviated offset on the pixel value. question: for ndr/cds mode, there is parasitic exposure in the suggested algorithm. can i do this algorithm instead? 1. reset row x 2. start integration timer 3. readout row x 4. reset row x+1 5. readout row x+1 6. reset row x+2 7. readout row x+2 8. (repeat to region of interest) 9. (wait for integration timer completion) 10. readout row x 11. (wait for time to reset a row) 12. readout row x+1 13. (wait for time to reset a row) 14. readout row x+2 15. (wait for time to reset a row) 16. (repeat to region of interest) answer: this algorithm can be used. question: our target application requires that we operate with the sun in our field of view. from initial calculations, this means that we can have a sun spot on the sensor around 50 pixels in diameter, over -exposed by a factor of ~1000 against other target spots. ? what is the role of the anti-blooming ground pin (gnd_ab) and how does it impact the sensor behavior? ? is the anti-blooming capability sufficient to prevent any additional ?recovery? time of the sensor? ? what pixel to pixel crosstalk behavior can be expected around the sun spot? 9.8% of the full well (table 27 on page 23)? answer: when a pixel is saturated and even goes to negative voltage levels, it is not suitable for lower electro potential level to attract new photon-electrons. so the extra photo-electrons can now go to nearby pixels more easily than to the pixel where the electrons are generated. this is visible in the image as blooming. the anti-blooming method involves keeping the photo-diode at an attractive electro-potential that still attract new electrons. this is done by holding the gate of the reset transistor higher then ground level. the ?row_select? line that selects a specific row of the pixel array is a digital signal that swaps between ?gnd_dig? and ?vdd_dig?. the ?row_reset? line that resets a specific row of pixels uses the same drivers as the ?row_select? line but the lower voltage level is not ?gnd_dig? but ?gnd_ab?. so the lower level of gate of the pixel reset transistor can be set by adapting the voltage level of ?gnd_ab?. it is recommended not to go higher than 1 v with the voltage level of ?gnd_ab? than 1 v. the digital circuits of the sensor should still see it as a digital ?0?. some second order effect of keeping gnd_ab higher than ground: ? the swing of row_reset is now lower. this means less cross-talk to the photo-diode and higher dark-level. probably you don?t see much changes if you read the sensor in dual sampling. both the signal and the dark reference changes in level, so the subtraction is still the same. but you use the photo-diode on a slightly higher voltage level. therefore, the pixel cap can be a little lower. (nonlinear behavior of the cap of a diode). ? the swing of the diode is also lowered, but probably only the part of the swing that was not read-out anyway. it is very difficult to get any quantification of the anti-blooming ef fect. the best way of figuring is just trying it. the anti-blooming function is not part of the characterization of the sensor.
NOIH2SM1000A www.onsemi.com 64 question: i am trying to estimate the pulse height distribution (phd) from electrons and protons traversing the focal plane array. the phd is the probability of seeing a pulse of a given size in a single pixel from an electron or proton coming from a random direction and striking in a random location. when an electron traverses a unit cell it excites electrons. the total amount of charge is proportional to the length of the path (the chord length) through the unit cell. charge that is created outside the collection region of the detector has little effect. the charge in the photodiode is collected and looks similar to a signal. to calculate the chord length distribution through the photodiode i need its dimensions. i have been assuming that it is 7.5 microns on a side, living within the 15 micron unit cell. what is the thickness of the collection region. it can be quite thick, but i have been assuming a fairly thin geometry. the production of streaks by protons is sensitive to the thickness of the photodiode as well (thicker means longer streaks). so i think the answer to your question is that i need all three dimensions of the photodiodes in the array. are the unit cells repeated across the array or are they arranged with mirror images next to each other, which makes the light sensitive regions cluster in groups of two or four. answer:
NOIH2SM1000A www.onsemi.com 65 question: will pixel-to-pixel crosstalk only appear if a pixel is fully saturated? or will it also appear if for instance the pixel is only as half it?s full well capacity. if it does happen even if the pixel is not fully saturated do you know to what extent it will happen - will it also be the same extent as shown in pixel ? to ? pixel cross talk on page 34 of your data sheet? will pixel-to-pixel crosstalk only lead to charge leaking from a pixel with higher signal to a pixel with low signal or vice versa? answer: the pixel-to-pixel crosstalk shown in pixel ? to ? pixel cross talk on page 34 is cross-talk caused by floating generated electrons that are not yet captured by any photo-diode. so it has nothing to do with the actual level on the accumulated photo-diodes. only when the photo-diode is really totally saturated, the floating electrons can behave differently. the saturated photo-diode cannot capture more electrons, so incoming electrons are not kept. the generated electrons will be captured by neighboring photo-diodes that are not yet completely saturated (or recombined). so cross-talk as measured in pixel ? to ? pixel cross talk on page 34 goes both from pixel with higher to lower signal levels and vice versa. it doesn?t matter as long they are not fully saturated. note that the anti-blooming ground can keep the pixel out of a completely saturation state. question: the test results after proton beam are not as expected. to interpret the results we want to know what the thickness is of the epitaxial layer. or more in detail the thickness of the active area of the photo diode. answer: epi thickness: 5 m, the nwell is about 1 m deep. question: how large is the active area compared to the overall pixel? almost the whole photo-sensitive area is active area. answer: 96% of the whole pixel is active area. everything expect the transistors and nwell, is p-doped question: is there a spice model available for the radiation hard pixel used in the has device? answer: no. the models that are used are just non-radiation hard models. question: what is the penetration depth of photons in the has2 pixel versus the spectral range? doe we have such graphs available? answer: this is theory. we have penetration versus spectral range but this depends on the actual doping levels of the substrate. so it is never actual measured. question: how does the mtf behave with increasing wavelength? is there an mtf graph available versus spectral range? answer: you can expect a large decrease in mtf when using higher wavelengths. to known how it behaves on the has2, new mtf measurements are needed. question: in chapter 6.2 of the actual data sheet it is suggested to use one regulator for all digital supply pins together, one regulator for the sensor core analog supplies together, and one regulator for the adc analog supply. against it the test circuit in chapter 7.3 uses 5 different supply voltages (vddd, vdda, vpix, vadca, vadcd). with the first information i decided to use 3 regulators: one for vdd_ana + vdd_pix, one for vdd_dig + vdd_adc_dig and one only for vdd_adc_ana. moreover i use two grounds (analog and digital). sadly with this configuration i have some problems in window-mode. every 2nd line of the first lines of a window overshoot there. the more lines are sampled the lower is that effect. after may be 20 to 30 lines the effect exists no longer. in an other pcb i use a separate regulator for vdd_pix instead for vdd_adc_ana (vdd_adc_ana is connected to vdd_ana) and everything works fine. is that the problem? answer: i expect that the peak currents of vpix make the power regulator that you use unstable. this is no problem as long the vpix isn?t use by other parts of the sensor. so it is normal that when vpix has its own regulator, nothing strange becomes visible in the image. but probably, vpix is still not stable. however, the double sampling (both the signal and the black level are affected by the voltage level of vpix) hide the problem for you. addendum an-aps-ff-wo-06-001 (v1.): application note on has readout methods
NOIH2SM1000A www.onsemi.com 66 optical quality ? definitions the following definitions and limits are used to define the optical quality of the has2 type variants as outlined in table 10 on page 9. dead pixel a dead pixel is a pixel that has no electrical response. in the image, this results in a pixel with fixed adc value. the number of pixels with adc value 0 are count and accumulated. bright pixel in fpn image a fpn image is a dark image with the shortest possible integration time. a bright pixel in this image is a pixel with an adc value higher than 20% of the full range of the entire pixel array. bad pixel in prnu image a prnu image is an image where all pixels have a 50% response of the full range of the entire pixel array. a bad pixel in this image is a pixel with an adc value that dif fers more than 10% of the average response. this average response can be calculated on the total pixel array for a global measurement or on 32 x 32 pixels for a local measurement. bad row/column a bad row/column is detected in the prnu image. a row/column is defective when it differs more than 5% from the average of a moving window of 32 rows/columns. a row/column is also defined as defective when it has 100 or more adjacent bad, bright, or dead pixels. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NOIH2SM1000A/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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